PowerQUICC ProcessorsのトピックMPC885 GPCM and UPM

MPC885 GPCM and UPM

KobyKluger — Wed, 03 Nov 2021 06:08:27 GMT

I am using MPC885 (formerly FreeScale) with its GPCM used for controlling peripheral devices and its UPM used for operating an SDRAM.

My question is: How can I insert some delay between the GPCM end of cycle and UPM beginning of cycle?

Bulat — Thu, 04 Nov 2021 02:50:25 GMT

The processor allows to add one bus clock cycle between GPCM read cycle and subsequent bus transaction. ORx[EHTR] bit should be set for GPCM bank.

If for some reason you need greater delay, you can program UPM read/write patterns with shifted/delayed CS assertion.

KobyKluger — Thu, 11 Nov 2021 09:44:00 GMT

I tried setting EHTR bit to "1" but it doesn't have any impact on the delay between GPCM and UPM.

The refrence manual states explicitley that EHTR bit refers to GPCM only, but it doesn't influence the delay when switching to UPM.

I wonder if anyway there is a way to insert more delay between the two machines without re-programming the UPM...