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    <title>topic Discrete DDR3L sdram in PowerQUICC Processors</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360374#M3909</link>
    <description>&lt;P&gt;Hi team,&lt;/P&gt;&lt;P&gt;Board: custom t2081&lt;/P&gt;&lt;P&gt;Ddr: mt41k512m16&lt;/P&gt;&lt;P&gt;Ddrclk:133.33mhz&lt;/P&gt;&lt;P&gt;Sysclk:66.66mhz&lt;/P&gt;&lt;P&gt;I have a query regarding DDR configuration and validation using QCVS tool.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;1. Can you guide me the settings needed to be used for discrete dram in QCVS tool.&lt;/P&gt;&lt;P&gt;2. Can DDR be used at different data rates since I have seen only one data rate setting in datasheet&amp;nbsp;&lt;/P&gt;&lt;P&gt;3. What value of mem_pll_rat should be set in rcw for 1866mt/s data rate of ddr because if I keep 7 as value it is not considering and 14 also.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any help regarding these three issues will be great.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks and regards&lt;/P&gt;&lt;P&gt;Irfan&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Sun, 24 Oct 2021 08:31:38 GMT</pubDate>
    <dc:creator>Irfan3</dc:creator>
    <dc:date>2021-10-24T08:31:38Z</dc:date>
    <item>
      <title>Discrete DDR3L sdram</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360374#M3909</link>
      <description>&lt;P&gt;Hi team,&lt;/P&gt;&lt;P&gt;Board: custom t2081&lt;/P&gt;&lt;P&gt;Ddr: mt41k512m16&lt;/P&gt;&lt;P&gt;Ddrclk:133.33mhz&lt;/P&gt;&lt;P&gt;Sysclk:66.66mhz&lt;/P&gt;&lt;P&gt;I have a query regarding DDR configuration and validation using QCVS tool.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;1. Can you guide me the settings needed to be used for discrete dram in QCVS tool.&lt;/P&gt;&lt;P&gt;2. Can DDR be used at different data rates since I have seen only one data rate setting in datasheet&amp;nbsp;&lt;/P&gt;&lt;P&gt;3. What value of mem_pll_rat should be set in rcw for 1866mt/s data rate of ddr because if I keep 7 as value it is not considering and 14 also.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any help regarding these three issues will be great.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks and regards&lt;/P&gt;&lt;P&gt;Irfan&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 24 Oct 2021 08:31:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360374#M3909</guid>
      <dc:creator>Irfan3</dc:creator>
      <dc:date>2021-10-24T08:31:38Z</dc:date>
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    <item>
      <title>Re: Discrete DDR3L sdram</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360376#M3910</link>
      <description>&lt;P&gt;1) What is the SDRAM configuration?&lt;/P&gt;&lt;P&gt;2) Yes, it is generally possible.&lt;/P&gt;&lt;P&gt;3) You wrote:&lt;/P&gt;&lt;P&gt;&amp;gt; if I keep 7 as value it is not considering&lt;/P&gt;&lt;P&gt;What do you mean?&lt;/P&gt;&lt;P&gt;Have you selected correct Silicon revision?&lt;/P&gt;</description>
      <pubDate>Sun, 24 Oct 2021 10:02:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360376#M3910</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2021-10-24T10:02:12Z</dc:date>
    </item>
    <item>
      <title>Re: Discrete DDR3L sdram</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360381#M3911</link>
      <description>&lt;P&gt;Hi ufedor,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for your quick response.&lt;/P&gt;&lt;P&gt;1. We are using single fixed discrete DDR. Single rank 8chips forming 4 gb of ddr&lt;/P&gt;&lt;P&gt;3. In rcw, for mem_pll_rat I had given 7 as value for obtaining 1866mt/s data rate and also tried 14 as mem_pll_ rat value. Silicon revision is 1.1&lt;/P&gt;&lt;P&gt;Thanks and regards&lt;/P&gt;&lt;P&gt;Irfan&lt;/P&gt;</description>
      <pubDate>Sun, 24 Oct 2021 11:34:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360381#M3911</guid>
      <dc:creator>Irfan3</dc:creator>
      <dc:date>2021-10-24T11:34:26Z</dc:date>
    </item>
    <item>
      <title>Re: Discrete DDR3L sdram</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360383#M3912</link>
      <description>&lt;P&gt;1) Use the DDR Wizard:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DDR wizard.jpg" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/159942iAB47805CC6C75DD8/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DDR wizard.jpg" alt="DDR wizard.jpg" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DDR wizard.jpg&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;3) You wrote:&lt;/P&gt;
&lt;P&gt;&amp;gt; In rcw, for mem_pll_rat I had given 7 as value for obtaining 1866mt/s data rate&lt;/P&gt;
&lt;P&gt;What is the result?&lt;/P&gt;</description>
      <pubDate>Sun, 24 Oct 2021 11:56:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360383#M3912</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2021-10-24T11:56:24Z</dc:date>
    </item>
    <item>
      <title>Re: Discrete DDR3L sdram</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360386#M3913</link>
      <description>&lt;P&gt;Hi ufedor,&lt;/P&gt;&lt;P&gt;Thanks a lot for spending your valuable time in answering my queries.&lt;/P&gt;&lt;P&gt;1. According to this image I see the data rate at controller side and speed rating at dram settings are different. Any reason for that. And for the skews can you please give me a hint on how to get it as I don't have knowledge of hardware PCBs&amp;nbsp;&lt;/P&gt;&lt;P&gt;3. I tried on custom board as well as t2080rdb both were not supporting and were throwing error as "d_init not cleared. Memory may not work". So there is a confusion as to what value to take in rcw to obtain 1866mt/s data rate.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks and regards&lt;/P&gt;&lt;P&gt;Irfan&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 24 Oct 2021 12:22:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360386#M3913</guid>
      <dc:creator>Irfan3</dc:creator>
      <dc:date>2021-10-24T12:22:55Z</dc:date>
    </item>
    <item>
      <title>Re: Discrete DDR3L sdram</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360400#M3914</link>
      <description>&lt;P&gt;1) What is the SDRAM devices data rate in your case?&lt;/P&gt;
&lt;P&gt;You wrote:&lt;/P&gt;
&lt;P&gt;&amp;gt; for the skews can you please give me a hint on how to get it as&lt;/P&gt;
&lt;P&gt;&amp;gt; I don't have knowledge of hardware PCBs&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Please ask the board designer.&lt;/P&gt;
&lt;P&gt;3) What exactly you have done on the T2080RDB and what are the results?&lt;/P&gt;</description>
      <pubDate>Sun, 24 Oct 2021 17:29:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360400#M3914</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2021-10-24T17:29:43Z</dc:date>
    </item>
    <item>
      <title>Re: Discrete DDR3L sdram</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360691#M3917</link>
      <description>&lt;P&gt;Hi Ufedor,&lt;/P&gt;&lt;P&gt;3) i modified the RCW for DDR and loaded in the NOR flash at E8000000 through code warrior. After that i tried to power up the board, then i was getting this error " D_INIT not cleared. Memory may not work".&lt;/P&gt;&lt;P&gt;1). what about this questoin "According to this image I see the data rate at controller side and speed rating at dram settings are different. Any reason for that" is it a example which you have shared with me or a working configuration?&lt;/P&gt;&lt;P&gt;thanks &amp;amp;&amp;nbsp; regards&lt;/P&gt;&lt;P&gt;irfan&lt;/P&gt;</description>
      <pubDate>Mon, 25 Oct 2021 08:12:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360691#M3917</guid>
      <dc:creator>Irfan3</dc:creator>
      <dc:date>2021-10-25T08:12:21Z</dc:date>
    </item>
    <item>
      <title>Re: Discrete DDR3L sdram</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360775#M3921</link>
      <description>&lt;P&gt;1) You wrote:&lt;/P&gt;
&lt;P&gt;&amp;gt; Any reason for that.&lt;/P&gt;
&lt;P&gt;No special reason - just a possible case.&lt;/P&gt;
&lt;P&gt;&amp;gt; And for the skews can you please give me a hint on&lt;/P&gt;
&lt;P&gt;&amp;gt; how to get it as I don't have knowledge of hardware PCBs&lt;/P&gt;
&lt;P&gt;For the discrete SDRAM memory the information about DDR interface signals PCB traces lengths has to be provided by the board designer.&lt;/P&gt;
&lt;P&gt;3) Please provide T2080RDB U-Boot booting log.&lt;/P&gt;</description>
      <pubDate>Mon, 25 Oct 2021 09:46:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360775#M3921</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2021-10-25T09:46:57Z</dc:date>
    </item>
    <item>
      <title>Re: Discrete DDR3L sdram</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360786#M3922</link>
      <description>&lt;P&gt;Hi Ufedor,&lt;/P&gt;&lt;P&gt;Thanks alot. i will try with the image settings.&lt;/P&gt;&lt;P&gt;one more thing in the properties window of DDR configuration some of the parameters were available in the datasheet whereas 50% of them were not available. so is it necessary to get all values and feed in the properties window or we can consider some default parameters and try validation.&lt;/P&gt;&lt;P&gt;thanks &amp;amp; regards,&lt;/P&gt;&lt;P&gt;irfan&lt;/P&gt;</description>
      <pubDate>Mon, 25 Oct 2021 10:05:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360786#M3922</guid>
      <dc:creator>Irfan3</dc:creator>
      <dc:date>2021-10-25T10:05:39Z</dc:date>
    </item>
    <item>
      <title>Re: Discrete DDR3L sdram</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360833#M3923</link>
      <description>&lt;P&gt;3) You wrote:&lt;/P&gt;&lt;P&gt;&amp;gt; i modified the RCW for DDR and loaded in the NOR flash at E8000000 through code warrior.&lt;/P&gt;&lt;P&gt;Please provide binary image of the RCW for inspection.&lt;/P&gt;&lt;P&gt;4) What is the processor revision on the T2080RDB?&lt;/P&gt;</description>
      <pubDate>Mon, 25 Oct 2021 11:50:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360833#M3923</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2021-10-25T11:50:19Z</dc:date>
    </item>
    <item>
      <title>Re: Discrete DDR3L sdram</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360840#M3924</link>
      <description>&lt;P&gt;Hi Ufedor,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;3) I am attaching the RCW which was used for 1866MT/s data rate for DDR&lt;/P&gt;&lt;P&gt;4) processor revision is 1.1&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks &amp;amp; regards&lt;/P&gt;&lt;P&gt;irfan&lt;/P&gt;</description>
      <pubDate>Mon, 25 Oct 2021 12:04:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360840#M3924</guid>
      <dc:creator>Irfan3</dc:creator>
      <dc:date>2021-10-25T12:04:44Z</dc:date>
    </item>
    <item>
      <title>Re: Discrete DDR3L sdram</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360841#M3925</link>
      <description>&lt;P&gt;Hi Ufedor,&lt;/P&gt;&lt;P&gt;one more thing in the properties window of DDR configuration some of the parameters were available in the datasheet whereas 50% of them were not available. so is it necessary to get all values and feed in the properties window or we can consider some default parameters and try validation.&lt;/P&gt;&lt;P&gt;thanks &amp;amp; regards,&lt;/P&gt;&lt;P&gt;irfan&lt;/P&gt;</description>
      <pubDate>Mon, 25 Oct 2021 12:07:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360841#M3925</guid>
      <dc:creator>Irfan3</dc:creator>
      <dc:date>2021-10-25T12:07:00Z</dc:date>
    </item>
    <item>
      <title>Re: Discrete DDR3L sdram</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360981#M3926</link>
      <description>&lt;P&gt;The following Wizard settings should be used for the T2080RDB board:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="DDRv Wizard.jpg" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/160047iE9CCBFBE685C2241/image-size/medium?v=v2&amp;amp;px=400" role="button" title="DDRv Wizard.jpg" alt="DDRv Wizard.jpg" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;DDRv Wizard.jpg&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt; &lt;/P&gt;</description>
      <pubDate>Mon, 25 Oct 2021 17:13:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Discrete-DDR3L-sdram/m-p/1360981#M3926</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2021-10-25T17:13:34Z</dc:date>
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