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    <title>topic DDR initialization and configuration for fixed DRAM in PowerQUICC Processors</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/DDR-initialization-and-configuration-for-fixed-DRAM/m-p/1339225#M3855</link>
    <description>&lt;P&gt;Hi Team,&lt;/P&gt;&lt;P&gt;I am currently trying to initialize fixed DRAM on my custom board.&lt;/P&gt;&lt;P&gt;For this i am following the QCVS tool user guide. based on this guide i have created a project and selected parameters as Fixed DRAM, speed, rank etc in project creation window.&lt;/P&gt;&lt;P&gt;in the properties window i have made modification according to the AN4039 document and have generated the processor code. but when i try to do validation in which the first step is operational DDR test (which is to check for hardware connection) is failing.&lt;/P&gt;&lt;P&gt;It is throwing error as "&lt;STRONG&gt;Error configuring the target! - DDR initialization failed: D_INIT was not cleared by hardware&lt;/STRONG&gt;". so Team, what could be the issue for this error.&lt;/P&gt;&lt;P&gt;Is DDR initialization and validation dependent on RCW values?&lt;/P&gt;&lt;P&gt;FYI, in ERR_DETECT register the ACE bit is 0.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can you please suggest me what to do to solve this error?&lt;/P&gt;</description>
    <pubDate>Mon, 13 Sep 2021 16:07:36 GMT</pubDate>
    <dc:creator>Irfan3</dc:creator>
    <dc:date>2021-09-13T16:07:36Z</dc:date>
    <item>
      <title>DDR initialization and configuration for fixed DRAM</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/DDR-initialization-and-configuration-for-fixed-DRAM/m-p/1339225#M3855</link>
      <description>&lt;P&gt;Hi Team,&lt;/P&gt;&lt;P&gt;I am currently trying to initialize fixed DRAM on my custom board.&lt;/P&gt;&lt;P&gt;For this i am following the QCVS tool user guide. based on this guide i have created a project and selected parameters as Fixed DRAM, speed, rank etc in project creation window.&lt;/P&gt;&lt;P&gt;in the properties window i have made modification according to the AN4039 document and have generated the processor code. but when i try to do validation in which the first step is operational DDR test (which is to check for hardware connection) is failing.&lt;/P&gt;&lt;P&gt;It is throwing error as "&lt;STRONG&gt;Error configuring the target! - DDR initialization failed: D_INIT was not cleared by hardware&lt;/STRONG&gt;". so Team, what could be the issue for this error.&lt;/P&gt;&lt;P&gt;Is DDR initialization and validation dependent on RCW values?&lt;/P&gt;&lt;P&gt;FYI, in ERR_DETECT register the ACE bit is 0.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can you please suggest me what to do to solve this error?&lt;/P&gt;</description>
      <pubDate>Mon, 13 Sep 2021 16:07:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/DDR-initialization-and-configuration-for-fixed-DRAM/m-p/1339225#M3855</guid>
      <dc:creator>Irfan3</dc:creator>
      <dc:date>2021-09-13T16:07:36Z</dc:date>
    </item>
    <item>
      <title>Re: DDR initialization and configuration for fixed DRAM</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/DDR-initialization-and-configuration-for-fixed-DRAM/m-p/1339454#M3856</link>
      <description>&lt;P&gt;What is NXP device you are asking about?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 14 Sep 2021 04:31:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/DDR-initialization-and-configuration-for-fixed-DRAM/m-p/1339454#M3856</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2021-09-14T04:31:44Z</dc:date>
    </item>
    <item>
      <title>Re: DDR initialization and configuration for fixed DRAM</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/DDR-initialization-and-configuration-for-fixed-DRAM/m-p/1339455#M3857</link>
      <description>&lt;P&gt;Hi Bulat,&lt;/P&gt;&lt;P&gt;Thanks for your quick response.&lt;/P&gt;&lt;P&gt;I am using T2081 as reference for my custom board.&lt;/P&gt;&lt;P&gt;currently i am using QCVS tool for initializing, configuring and validation of DDR with reference of QCVS tool user guide but as mentioned earlier i am getting that error.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;can you please suggest me what to do to solve this error?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks and&amp;nbsp; Regards&lt;/P&gt;&lt;P&gt;Irfan&lt;/P&gt;</description>
      <pubDate>Tue, 14 Sep 2021 04:40:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/DDR-initialization-and-configuration-for-fixed-DRAM/m-p/1339455#M3857</guid>
      <dc:creator>Irfan3</dc:creator>
      <dc:date>2021-09-14T04:40:57Z</dc:date>
    </item>
    <item>
      <title>Re: DDR initialization and configuration for fixed DRAM</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/DDR-initialization-and-configuration-for-fixed-DRAM/m-p/1339928#M3862</link>
      <description>&lt;P&gt;Error message means that DDR is not functional. Many reasons can cause it, mistakes in the schematics, mistakes in the RCW, board level issues, incorrect DDR sw setup, problems with power supplies, including MVREF.&lt;/P&gt;
&lt;P&gt;First I would recommend to check if the proper clock signal with expected frequency appears at the SDRAM clock pins after DDR initilalization. Use a scope for that.&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Bulat&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 14 Sep 2021 17:16:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/DDR-initialization-and-configuration-for-fixed-DRAM/m-p/1339928#M3862</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2021-09-14T17:16:27Z</dc:date>
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