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    <title>topic MPC8548E Memory Map CCSR in PowerQUICC Processors</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8548E-Memory-Map-CCSR/m-p/252272#M372</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have a question about the&amp;nbsp; CCSR Register&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the documentations says&lt;/P&gt;&lt;P&gt;“&lt;SPAN style="font-size: 12pt; font-family: 'Times New Roman','serif';"&gt;&lt;EM&gt;All of the memory mapped configuration, control, and status registers in the MPC8548E are contained&lt;/EM&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12pt; font-family: 'Times New Roman','serif';"&gt;&lt;EM&gt;within a 1-Mbyte address region. To allow for flexibility, the configuration, control, and status block is&lt;/EM&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;SPAN style="font-family: 'Times New Roman','serif'; font-size: 12pt;"&gt;relocatable in the local address space.&lt;/SPAN&gt;” ‘Section 2.3 Reference Manual.&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What is the process to relocate this register? When and How it is done?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 21 Feb 2014 19:56:24 GMT</pubDate>
    <dc:creator>axlmr</dc:creator>
    <dc:date>2014-02-21T19:56:24Z</dc:date>
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      <title>MPC8548E Memory Map CCSR</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8548E-Memory-Map-CCSR/m-p/252272#M372</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have a question about the&amp;nbsp; CCSR Register&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the documentations says&lt;/P&gt;&lt;P&gt;“&lt;SPAN style="font-size: 12pt; font-family: 'Times New Roman','serif';"&gt;&lt;EM&gt;All of the memory mapped configuration, control, and status registers in the MPC8548E are contained&lt;/EM&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-size: 12pt; font-family: 'Times New Roman','serif';"&gt;&lt;EM&gt;within a 1-Mbyte address region. To allow for flexibility, the configuration, control, and status block is&lt;/EM&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;SPAN style="font-family: 'Times New Roman','serif'; font-size: 12pt;"&gt;relocatable in the local address space.&lt;/SPAN&gt;” ‘Section 2.3 Reference Manual.&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What is the process to relocate this register? When and How it is done?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 21 Feb 2014 19:56:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8548E-Memory-Map-CCSR/m-p/252272#M372</guid>
      <dc:creator>axlmr</dc:creator>
      <dc:date>2014-02-21T19:56:24Z</dc:date>
    </item>
    <item>
      <title>Re: MPC8548E Memory Map CCSR</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8548E-Memory-Map-CCSR/m-p/252273#M373</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The process is documented in the "Updating CCSRBAR" section of the manual (4.3.1.1.1).&amp;nbsp; It is typically done during early boot if the default address isn't desired (e.g. if you want to use 4GiB or more of RAM, you'll want to move CCSR out of the way).&amp;nbsp; U-Boot has code to relocate CCSRBAR in arch/powerpc/cpu/mpc85xx/start.S.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Feb 2014 19:00:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8548E-Memory-Map-CCSR/m-p/252273#M373</guid>
      <dc:creator>scottwood</dc:creator>
      <dc:date>2014-02-25T19:00:48Z</dc:date>
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