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    <title>topic RCW(Reset Configuration Words) Sources for MPC8349E in PowerQUICC Processors</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/RCW-Reset-Configuration-Words-Sources-for-MPC8349E/m-p/1266475#M3663</link>
    <description>&lt;P&gt;Hello, NXP engineers and all members of the community group.&lt;/P&gt;&lt;P&gt;I am working on a new board development using the MPC8394E processor.&lt;BR /&gt;Various other configurations were designed by getting a reference through the EVM board, etc.&lt;/P&gt;&lt;P&gt;I have additional questions.&lt;/P&gt;&lt;P&gt;According to the document AN2931,&lt;BR /&gt;If RCW is stored in a flash on the local bus like our system, there is an issue that the CPU core does not work because during the PORESET process, the device cannot read the RCW value before the valid RCW value is written to the flash.&lt;/P&gt;&lt;P&gt;In this case, there are 3 options.&lt;/P&gt;&lt;P&gt;Among them, first of all, if the RCW value is read with the hard-coded option, is this value saved in the boot loader?&lt;/P&gt;&lt;P&gt;Also, in the case of the hard-coded option, the device is shown to operate in PCI agent mode.&lt;/P&gt;&lt;P&gt;As in the previous inquiry,&amp;nbsp;all peripherals are controlled through specific controllers or local bus controller and our system will not use the PCI bus at all.&lt;/P&gt;&lt;P&gt;Wouldn't it be a problem to the system operation even if booted in PCI agent mode?&lt;/P&gt;&lt;P&gt;Secondly, as designed as BCSR in the MPC8349EAMDSPB, if RCW value is provided as logic through CPLD or FPGA during POR, is this value input through the local bus?&lt;BR /&gt;Before the device core wakes up, is it possible to access the local bus and read the values written to the FPGA?&lt;/P&gt;&lt;P&gt;Please answer about my question.&lt;/P&gt;</description>
    <pubDate>Thu, 22 Apr 2021 09:48:52 GMT</pubDate>
    <dc:creator>youngho_cho</dc:creator>
    <dc:date>2021-04-22T09:48:52Z</dc:date>
    <item>
      <title>RCW(Reset Configuration Words) Sources for MPC8349E</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/RCW-Reset-Configuration-Words-Sources-for-MPC8349E/m-p/1266475#M3663</link>
      <description>&lt;P&gt;Hello, NXP engineers and all members of the community group.&lt;/P&gt;&lt;P&gt;I am working on a new board development using the MPC8394E processor.&lt;BR /&gt;Various other configurations were designed by getting a reference through the EVM board, etc.&lt;/P&gt;&lt;P&gt;I have additional questions.&lt;/P&gt;&lt;P&gt;According to the document AN2931,&lt;BR /&gt;If RCW is stored in a flash on the local bus like our system, there is an issue that the CPU core does not work because during the PORESET process, the device cannot read the RCW value before the valid RCW value is written to the flash.&lt;/P&gt;&lt;P&gt;In this case, there are 3 options.&lt;/P&gt;&lt;P&gt;Among them, first of all, if the RCW value is read with the hard-coded option, is this value saved in the boot loader?&lt;/P&gt;&lt;P&gt;Also, in the case of the hard-coded option, the device is shown to operate in PCI agent mode.&lt;/P&gt;&lt;P&gt;As in the previous inquiry,&amp;nbsp;all peripherals are controlled through specific controllers or local bus controller and our system will not use the PCI bus at all.&lt;/P&gt;&lt;P&gt;Wouldn't it be a problem to the system operation even if booted in PCI agent mode?&lt;/P&gt;&lt;P&gt;Secondly, as designed as BCSR in the MPC8349EAMDSPB, if RCW value is provided as logic through CPLD or FPGA during POR, is this value input through the local bus?&lt;BR /&gt;Before the device core wakes up, is it possible to access the local bus and read the values written to the FPGA?&lt;/P&gt;&lt;P&gt;Please answer about my question.&lt;/P&gt;</description>
      <pubDate>Thu, 22 Apr 2021 09:48:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/RCW-Reset-Configuration-Words-Sources-for-MPC8349E/m-p/1266475#M3663</guid>
      <dc:creator>youngho_cho</dc:creator>
      <dc:date>2021-04-22T09:48:52Z</dc:date>
    </item>
    <item>
      <title>Re: RCW(Reset Configuration Words) Sources for MPC8349E</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/RCW-Reset-Configuration-Words-Sources-for-MPC8349E/m-p/1267305#M3666</link>
      <description>&lt;P style="margin-bottom: 0in; line-height: 100%; orphans: 0; widows: 0;"&gt;&lt;FONT face="DejaVu Sans, sans-serif"&gt;&lt;FONT size="2" style="font-size: 11pt;"&gt;&lt;FONT color="#000000"&gt;&lt;SPAN&gt;There are several hard-coded default options, selected by the reset configuration input signals, CFG_RESET_SOURCE[0:2]. Hard-coded reset configuration words are driven internally and and do not appear on any MPC834x interface. All hard-coded configuration words set &lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P style="margin-bottom: 0in; line-height: 100%; orphans: 0; widows: 0;"&gt;&lt;FONT face="DejaVu Sans, sans-serif"&gt;&lt;FONT size="2" style="font-size: 11pt;"&gt;&lt;FONT color="#000000"&gt;&lt;SPAN&gt;PCIHOST=0 PCI agent mode&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P style="margin-bottom: 0in; line-height: 100%; orphans: 0; widows: 0;"&gt;&lt;FONT face="DejaVu Sans, sans-serif"&gt;&lt;FONT size="2" style="font-size: 11pt;"&gt;&lt;FONT color="#000000"&gt;&lt;SPAN&gt;PCI1ARB=0 External arbiter is used.&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P style="margin-bottom: 0in; line-height: 100%; orphans: 0; widows: 0;"&gt;&lt;FONT face="DejaVu Sans, sans-serif"&gt;&lt;FONT size="2" style="font-size: 11pt;"&gt;&lt;FONT color="#000000"&gt;&lt;SPAN&gt;COREDIS=1 e300c1 core is disabled (boot holdoff)&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P style="margin-bottom: 0in; line-height: 100%; orphans: 0; widows: 0;"&gt;&lt;FONT face="DejaVu Sans, sans-serif"&gt;&lt;FONT size="2" style="font-size: 11pt;"&gt;&lt;FONT color="#000000"&gt;&lt;SPAN&gt;BOOTSEQ=00 Boot sequencer is disabled&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P style="margin-bottom: 0in; line-height: 100%; orphans: 0; widows: 0;"&gt;&lt;FONT face="DejaVu Sans, sans-serif"&gt;&lt;FONT size="2" style="font-size: 11pt;"&gt;&lt;FONT color="#000000"&gt;&lt;SPAN&gt;More details you can find in the section &lt;/SPAN&gt;&lt;/FONT&gt;&lt;FONT color="#000000"&gt;&lt;SPAN&gt;&lt;SPAN style="font-weight: normal;"&gt;4.4.3.3 Default Reset Configuration Words of the MPC8349 reference manual&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P style="margin-bottom: 0in; line-height: 100%; orphans: 0; widows: 0;"&gt;&lt;FONT face="DejaVu Sans, sans-serif"&gt;&lt;FONT size="2" style="font-size: 11pt;"&gt;&lt;FONT color="#000000"&gt;&lt;SPAN&gt;These setting can be &lt;/SPAN&gt;&lt;/FONT&gt;&lt;SPAN style="font-variant: normal;"&gt;&lt;FONT color="#000000"&gt;&lt;SPAN style="letter-spacing: normal;"&gt;&lt;SPAN&gt;&lt;SPAN style="font-style: normal;"&gt;&lt;SPAN style="font-weight: normal;"&gt;unsolvable problem&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;FONT color="#000000"&gt;&lt;SPAN&gt; for your system if there is no external PCI host which can enable the core.&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P style="margin-bottom: 0in; line-height: 100%; orphans: 0; widows: 0;"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P style="margin-bottom: 0in; line-height: 100%; orphans: 0; widows: 0;"&gt;&lt;FONT face="DejaVu Sans, sans-serif"&gt;&lt;FONT size="2" style="font-size: 11pt;"&gt;&lt;FONT color="#000000"&gt;&lt;SPAN&gt;Typically RCW value from CPLD or FPGA during POR loaded using the local bus. Hoever if your FPGA has PCI host port then it can configure the MPC8349 PCI agent. &lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P style="margin-bottom: 0in; line-height: 100%; orphans: 0; widows: 0;"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P style="margin-bottom: 0in; line-height: 100%; orphans: 0; widows: 0;"&gt;&lt;FONT face="DejaVu Sans, sans-serif"&gt;&lt;FONT size="2" style="font-size: 11pt;"&gt;&amp;gt;Before the device core wakes up, is it possible to access the local bus and read the values written to the FPGA?&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P style="margin-bottom: 0in; line-height: 100%; orphans: 0; widows: 0;"&gt;&lt;FONT face="DejaVu Sans, sans-serif"&gt;&lt;FONT size="2" style="font-size: 11pt;"&gt;&lt;FONT color="#000000"&gt;&lt;SPAN&gt;&lt;SPAN style="font-weight: normal;"&gt;Yes it is possible.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/FONT&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 23 Apr 2021 14:12:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/RCW-Reset-Configuration-Words-Sources-for-MPC8349E/m-p/1267305#M3666</guid>
      <dc:creator>r8070z</dc:creator>
      <dc:date>2021-04-23T14:12:45Z</dc:date>
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