PowerQUICC Processors中的主题 MPC8378 DUART value read when RX FIFO is empty

MPC8378 DUART value read when RX FIFO is empty

EAlepins — Mon, 19 Oct 2020 21:50:01 GMT

Hi,

With MPC8378 DUART module, what value will be read from the RX FIFO if it is empty? (i.e. what is URBR value when ULSR[DR]=0 or UDSR[RXRDY]=1). I'm interested in FIFO mode. Whatever the DMA mode is.

Thanks,

Étienne

Re: MPC8378 DUART value read when RX FIFO is empty

Pavel — Tue, 20 Oct 2020 03:22:11 GMT

Usually the last character will be read from DUART FIFO if DUART FIFO is empty.

Re: MPC8378 DUART value read when RX FIFO is empty

EAlepins — Tue, 20 Oct 2020 12:00:31 GMT

Hi,

Thanks for your quick answer. Why do you say "usually"? Could you confirm on a board that behavior?

It makes a huge difference in my design. Indeed, I want to process the DUART data without intervention of the core (without interrupts) by using a DMA that will pop at a fixed rate the words received, even if there are no new words. Then SW, will analyze all the words and discard those which are false words. If reading an empty FIFO returns 0x00 or 0xFF for example, then I can manage to never send that kind of data. However, if the last word is returned, then I'll have to make my sent data vary each time to be able to detect false words.

Thanks,

Étienne

Re: MPC8378 DUART value read when RX FIFO is empty

Pavel — Wed, 21 Oct 2020 02:55:53 GMT

Data from empty FIFO is not specified.

Use the UFCR register for setting a receiver FIFO trigger level to control the received data available interrupt, and select the type of DMA signaling.

See the Section 22.3.1.6 in the MPC8379 Reference Manual.

Re: MPC8378 DUART value read when RX FIFO is empty

EAlepins — Wed, 21 Oct 2020 12:14:56 GMT

Hi,

Data from empty FIFO is not specified.

That's the point. That's why I am opening a support question. Could you ask design team what the behavior is?

UFCR[RTL] won't help since in my system won't use interrupts. It will rather use a timer-controlled DMA which will pull-out of the DUART's RX FIFO bytes at the same rate as the rate on the physical line. That's the only method we found to avoid SW overhead and complexity of using interrupts that frequently switches the applications context to/from an ISR.

Thanks,

Étienne