topic Re: DDR DRAM mode register address bits in PowerQUICC Processors

DDR DRAM mode register address bits

dallasclow — Mon, 29 Jun 2020 01:41:29 GMT

Are the bank address bits of the mode register settings (two msb's) of each field in DDR_SDRAM_MODE and DDR_SDRAM_MODE_2 used by the DDR controller at initialization or are they ignored? There is a separate field for each specific mode register, which should allow the bank address bits to be ignored when addressing the DRAMs. We're trying to assess the impact of a SW bug that incorrectly set the two msb's of the ESDMODE, ESDMODE2, and ESDMODE3 fields. Would these to bits be ignored or cause incorrect DRAM mode register writes?

Re: DDR DRAM mode register address bits

ufedor — Mon, 29 Jun 2020 07:26:48 GMT

Which processor is in question?

Re: DDR DRAM mode register address bits

dallasclow — Mon, 29 Jun 2020 16:12:56 GMT

This is an MPC8610.

Re: DDR DRAM mode register address bits

ufedor — Mon, 29 Jun 2020 16:34:58 GMT

> Would these to bits be ignored or cause incorrect DRAM mode register writes?

These bits are ignored.