https://community.nxp.com/t5/PowerQUICC-Processors/ODT-and-additive-latency/m-p/1096340#M3317 <HTML><HEAD></HEAD><BODY><P>Yes, CAS latency of 3, write latency of 2, and additive latency of 1 is ok to utilize ODT correctly.</P><P>RD_TO_PRE should be equal to tRTP,&nbsp; ADD_LAT should not be added.</P><P></P><P>Regards,</P><P>Bulat</P></BODY></HTML> Mon, 29 Jun 2020 09:03:29 GMT Bulat 2020-06-29T09:03:29Z https://community.nxp.com/t5/PowerQUICC-Processors/ODT-and-additive-latency/m-p/1096339#M3316 <HTML><HEAD></HEAD><BODY><P>The ODT_WR_CFG parameter of the CSn_CONFIG register indicates that write latency plus additive latency must be at least 3 to use ODT.&nbsp; Our application uses an MPC8610 with 64-bit DDR2 w/ECC running at 200 MHz (DDR400).&nbsp; Nominal CAS Latency is 3 and write latency is 2.&nbsp; ODT is required.&nbsp; Can CAS latency of 3, write latency of 2, and additive latency of 1 be used to meet this requirement and utilize ODT?&nbsp; If so, should the RD_TO_PRE field of the TIMING_CFG_2 register include the additive latency (1 additional clock) or should it just include the t_RTP duration (2 clocks) when additive latency is used?</P></BODY></HTML> Mon, 29 Jun 2020 01:40:23 GMT https://community.nxp.com/t5/PowerQUICC-Processors/ODT-and-additive-latency/m-p/1096339#M3316 dallasclow 2020-06-29T01:40:23Z https://community.nxp.com/t5/PowerQUICC-Processors/ODT-and-additive-latency/m-p/1096340#M3317 <HTML><HEAD></HEAD><BODY><P>Yes, CAS latency of 3, write latency of 2, and additive latency of 1 is ok to utilize ODT correctly.</P><P>RD_TO_PRE should be equal to tRTP,&nbsp; ADD_LAT should not be added.</P><P></P><P>Regards,</P><P>Bulat</P></BODY></HTML> Mon, 29 Jun 2020 09:03:29 GMT https://community.nxp.com/t5/PowerQUICC-Processors/ODT-and-additive-latency/m-p/1096340#M3317 Bulat 2020-06-29T09:03:29Z