PowerQUICC Processors中的主题 Re: DDR3 ECC Memory Connection

DDR3 ECC Memory Connection

aleksandrmaskin — Tue, 06 Aug 2013 08:52:59 GMT

Hello!

I've already written in Technical Support, but surely I get here a sooner answer. I've just started a new MPC8569E project. By the way, I had never dealt with Freescale processors before. I chose Micron 8-bit DDR3 memory to be EEC. It found out that it has a combined data mask and termination data strobe ball. How can I connect it to the DDR controller? Is it possible at all?

Thanks.

Re: DDR3 ECC Memory Connection

lunminliang — Wed, 07 Aug 2013 01:35:23 GMT

Hi, there is a document AN3940 Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces

http://cache.freescale.com/files/32bit/doc/app_note/AN3940.pdf?fsrch=1&sr=1

Re: DDR3 ECC Memory Connection

aleksandrmaskin — Wed, 07 Aug 2013 04:46:36 GMT

Hi, I found nothing concerning that their.

Maybe, I can make it without DM-signal in ECC?:smileyconfused:

Re: DDR3 ECC Memory Connection

lunminliang — Fri, 09 Aug 2013 02:31:27 GMT

HI, could you please send out the URL of the datasheet?

Re: DDR3 ECC Memory Connection

LewisTse — Thu, 15 Aug 2013 08:08:11 GMT

I suggest you should just disable the "termination data strobe" (TDQS) by setting the mode register. In other words the DM/TDQS will function as DM.

It seems TDQS is useful to provide a load as equivalent to using 4bit DDR. As our part does not support 4bit DDR at all, there is no point enabling the TDQS.

Re: DDR3 ECC Memory Connection

Bulat — Tue, 27 Aug 2013 06:27:09 GMT

No problem with combined DDR3's DM/TDQS pin, it should be connected to MPC8569's MDM[8] signal, i.e. Data Mask of the ECC byte. TDQS# signal of the SDRAM should be left floating. By default TDQS function is disabled on the SDRAM side, so the DM/TDQS pin functions as DM, and this is exactly what the MPC8569 needs for proper operations.

Re: DDR3 ECC Memory Connection

aleksandrmaskin — Wed, 04 Sep 2013 17:29:34 GMT

OK. I can send you datasheets in about a week.

Re: DDR3 ECC Memory Connection

aleksandrmaskin — Wed, 04 Sep 2013 17:30:28 GMT

Thank you, Lewis!:smileyhappy:

Re: DDR3 ECC Memory Connection

aleksandrmaskin — Wed, 04 Sep 2013 17:31:21 GMT

Thank you, Bulat!:smileygrin:

Re: DDR3 ECC Memory Connection

aleksandrmaskin — Wed, 04 Sep 2013 18:06:59 GMT

I uploaded the datasheet into my docs section. Hope, you can find it.

Re: DDR3 ECC Memory Connection

niranjanaradhya — Tue, 10 Sep 2013 07:11:39 GMT

Hi Bulat,

I am wonder there is no dedicated ddr reset ball on the MPC8569 IC, how to use the reset in this case for DDR3. and also where i can get the complete data sheet of MPC8569.

Re: DDR3 ECC Memory Connection

Bulat — Wed, 11 Sep 2013 04:04:32 GMT

We typically recommend to reset DDR3 devices with the same signal that is used to reset the MPC8569. You can also use a GPIO signal as DDR3 reset. In either case the reset signal going to DDR3 is required to be under DDR3 voltage rail, so a voltage converter like an open-drain circuit needs to be used.

Re: DDR3 ECC Memory Connection

niranjanaradhya — Wed, 11 Sep 2013 06:53:23 GMT

Thank you Bulat, where i can get complete data sheet for this part no.?

Re: DDR3 ECC Memory Connection

andrei_skok — Wed, 11 Sep 2013 10:27:54 GMT

It can be find on the MPC8569E Product Summary Page

Re: DDR3 ECC Memory Connection

aleksandrmaskin — Sun, 19 Jan 2014 12:13:36 GMT

hi, guys! I’ve got a new question. DDR3L memory chips have two Vttref (Vttca and Vttqe) inputs that should be fed with Vtt-voltage by means of separate traces. On the contrary, Freescale’s microcontroller has only one Vttref pin. What one of two traces should be connected to it?

Re: DDR3 ECC Memory Connection

Bulat — Mon, 20 Jan 2014 05:17:13 GMT

I would note that logical sequence is a bit different. I guess you have one VREF source on the board, this source should feed all Vttref inputs (typically using star topology). This includes MVREF of the processor, VREFDQ and VREFCA of the memory. Memory devices have independent VREFDQ and VREFCA inputs allowing to use different reference planes (GND or VDD) for signal routing. This is typically used on the DIMMs/SODIMMs, where data signals are referenced to GND plane, addrees/command/control - to VDD plane.

Re: DDR3 ECC Memory Connection

aleksandrmaskin — Mon, 20 Jan 2014 16:36:04 GMT

Hi, Bulat! Thank you for your response. Do you mean that situation? http://prntscr.com/2kzz1k To be honest, I draw both signals referenced to GND. And what is about processors MVREF? As I see, It doesn't matter how I route and decouple it? By the way, all my memory is on the board.

Re: DDR3 ECC Memory Connection

Bulat — Thu, 23 Jan 2014 04:41:23 GMT

Your scheme looks strange, and is difficult for comprehension (e.g. both VREFCA and VREFDQ go to D0-D7...). Only reasonable thing is a decoupling capacitor between VREFCA and VDD: yes, I meant this kind of VREFCA routing.

Since both REFs are referenced to GND you do not need two separate wires from VREF source to the memory, one is enough. MVREF signal of the processor must be referenced to GND, as well as all data group signals.

Re: DDR3 ECC Memory Connection

aleksandrmaskin — Fri, 24 Jan 2014 17:16:32 GMT

The scheme I uploaded is a fragment from SAMSUNG SO-DIMM scheme. I was in a hurry and didn't have a detailed look at it. OK, I see, a fly-by topology for Vref is also possible. Thank you again. I'm still confused when you are saying "signal referenced to the plane"... Does it mean that the signal trace are running over the GND/VDD plane a layer below?

Re: DDR3 ECC Memory Connection

Bulat — Sat, 25 Jan 2014 13:45:58 GMT

Yes, something like that. This is mostly applicable to data signals because they need to have a known impedance (typically 50-60 Ohm). For static signals like MVREF it is not so important, however it mean that decou[pling capacitors should be referenced to the same plane as associated signals. For processor's MVREF, memory's VREFDQ and data signals it is GND. For address/command/control signals and memory's VREFCA it is up to the designer.