<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic MPC5748G multi-core operation problem in PowerQUICC Processors</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC5748G-multi-core-operation-problem/m-p/1089851#M3302</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;When using Lauterbach to debug multi-core applications (first use In target reset, then run), both the z4_0 and z4_1 cores can run normally; but after removing the debugger, only z4_0 can run, while the z4_1 core cannot run normally. The code is modified by using "interrupt_control_multicore_mpc5748g" in SDK3.0RTM (CAN transceiver is added in Z4_1).&lt;BR /&gt;If you use Lauterbach's "Attach" function, you can see that Z4_ 1 is stuck in "IVOR1_Exception_Handler". How did this happen? I delayed 10000 times before Z4_1 initialized CAN, but it didn't work. Is the initialization timing wrong?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 13 Jul 2020 04:40:03 GMT</pubDate>
    <dc:creator>zhouwe</dc:creator>
    <dc:date>2020-07-13T04:40:03Z</dc:date>
    <item>
      <title>MPC5748G multi-core operation problem</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC5748G-multi-core-operation-problem/m-p/1089851#M3302</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;When using Lauterbach to debug multi-core applications (first use In target reset, then run), both the z4_0 and z4_1 cores can run normally; but after removing the debugger, only z4_0 can run, while the z4_1 core cannot run normally. The code is modified by using "interrupt_control_multicore_mpc5748g" in SDK3.0RTM (CAN transceiver is added in Z4_1).&lt;BR /&gt;If you use Lauterbach's "Attach" function, you can see that Z4_ 1 is stuck in "IVOR1_Exception_Handler". How did this happen? I delayed 10000 times before Z4_1 initialized CAN, but it didn't work. Is the initialization timing wrong?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 Jul 2020 04:40:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC5748G-multi-core-operation-problem/m-p/1089851#M3302</guid>
      <dc:creator>zhouwe</dc:creator>
      <dc:date>2020-07-13T04:40:03Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5748G multi-core operation problem</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC5748G-multi-core-operation-problem/m-p/1089852#M3303</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;if you can see that the code hangs in IVOR1 after "attach", first thing to check is the MCSRR0 core register. This register contains address of instruction which caused the error.&lt;/P&gt;&lt;P&gt;Anyway, could you share the project?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Lukas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 Jul 2020 12:14:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC5748G-multi-core-operation-problem/m-p/1089852#M3303</guid>
      <dc:creator>lukaszadrapa</dc:creator>
      <dc:date>2020-07-13T12:14:31Z</dc:date>
    </item>
  </channel>
</rss>

