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    <title>PowerQUICC Processors中的主题 MPC885 CAS latency</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC885-CAS-latency/m-p/1007645#M3124</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello'&lt;/P&gt;&lt;P&gt;I'm using MPC885 processor vxworks 6.3 operating system.&lt;/P&gt;&lt;P&gt;I'm trying to make UPM machine in romInit.s file work in SDRAM CAS Latency 3 instead of 2. I thought maybe somebody done this job and will save me a time.&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Eli&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 10 Mar 2020 06:14:58 GMT</pubDate>
    <dc:creator>eli_ochakovski</dc:creator>
    <dc:date>2020-03-10T06:14:58Z</dc:date>
    <item>
      <title>MPC885 CAS latency</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC885-CAS-latency/m-p/1007645#M3124</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello'&lt;/P&gt;&lt;P&gt;I'm using MPC885 processor vxworks 6.3 operating system.&lt;/P&gt;&lt;P&gt;I'm trying to make UPM machine in romInit.s file work in SDRAM CAS Latency 3 instead of 2. I thought maybe somebody done this job and will save me a time.&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Eli&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Mar 2020 06:14:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC885-CAS-latency/m-p/1007645#M3124</guid>
      <dc:creator>eli_ochakovski</dc:creator>
      <dc:date>2020-03-10T06:14:58Z</dc:date>
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    <item>
      <title>Re: MPC885 CAS latency</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC885-CAS-latency/m-p/1007646#M3125</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The following application note describe how to implement SDRAM interface on UPM:&lt;/P&gt;&lt;P&gt;&lt;A href="http://www.freescale.com/files/netcomm/doc/app_note/AN2066.pdf"&gt;http://www.freescale.com/files/netcomm/doc/app_note/AN2066.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also you could refer to the MPC885ADS Linux BSP containing UPM tables for SDRAM in U-Boot sources (u-boot\board\fads\fads.c):&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/products/processors-and-microcontrollers/legacy-mcu-mpus/powerquicc-processors/powerquicc-i-mpc8xx/powerquicc-processor-with-cpm-with-atm-usb-dual-10-100-ethernet-security:MPC885?tab=Design_Tools_Tab" title="https://www.nxp.com/products/processors-and-microcontrollers/legacy-mcu-mpus/powerquicc-processors/powerquicc-i-mpc8xx/powerquicc-processor-with-cpm-with-atm-usb-dual-10-100-ethernet-security:MPC885?tab=Design_Tools_Tab"&gt;PowerQUICC® Processor with CPM with ATM, USB, Dual 10/100 Ethernet, Security | NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Mar 2020 01:48:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC885-CAS-latency/m-p/1007646#M3125</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2020-03-11T01:48:08Z</dc:date>
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