<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>PowerQUICC ProcessorsのトピックRe: MPC8280 SDRAM  60x Bus配置问题</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8280-SDRAM-60x-Bus%E9%85%8D%E7%BD%AE%E9%97%AE%E9%A2%98/m-p/1005907#M3121</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;我看在AN2165中有个描述写的是在MPC8260A中“the MPC8260A (HiP4) and revision C of the MPC8260&amp;nbsp;can use these values but require an external multiplexer.”是否MPC8280CVVQLDA型号也是如此？&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 11 Nov 2019 09:24:31 GMT</pubDate>
    <dc:creator>lhb_will</dc:creator>
    <dc:date>2019-11-11T09:24:31Z</dc:date>
    <item>
      <title>MPC8280 SDRAM  60x Bus配置问题</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8280-SDRAM-60x-Bus%E9%85%8D%E7%BD%AE%E9%97%AE%E9%A2%98/m-p/1005905#M3119</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;在外面集成了两块SDRAM，型号是MT48LC4M32B2-。但是按照如下命令进行写时发现0x8地址的写入会修改0、0x10、0x1C地址的数据。请问可能是哪里没配置好？&lt;/P&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/92193iCB1EF6B9D79E325D/image-size/large?v=v2&amp;amp;px=999" title="sdram.jpg" alt="sdram.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Nov 2019 10:27:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8280-SDRAM-60x-Bus%E9%85%8D%E7%BD%AE%E9%97%AE%E9%A2%98/m-p/1005905#M3119</guid>
      <dc:creator>lhb_will</dc:creator>
      <dc:date>2019-11-05T10:27:22Z</dc:date>
    </item>
    <item>
      <title>Re: MPC8280 SDRAM  60x Bus配置问题</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8280-SDRAM-60x-Bus%E9%85%8D%E7%BD%AE%E9%97%AE%E9%A2%98/m-p/1005906#M3120</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;SDRAM memory chips require initialization sequence after power-on. Please look MPC8280 Reference Manual, Section&amp;nbsp;11.4.2 "SDRAM Power-On Initialization" for the exact sequence.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://www.nxp.com/docs/en/reference-manual/MPC8280RM.pdf"&gt;https://www.nxp.com/docs/en/reference-manual/MPC8280RM.pdf&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 10 Nov 2019 19:28:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8280-SDRAM-60x-Bus%E9%85%8D%E7%BD%AE%E9%97%AE%E9%A2%98/m-p/1005906#M3120</guid>
      <dc:creator>alexander_yakov</dc:creator>
      <dc:date>2019-11-10T19:28:14Z</dc:date>
    </item>
    <item>
      <title>Re: MPC8280 SDRAM  60x Bus配置问题</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8280-SDRAM-60x-Bus%E9%85%8D%E7%BD%AE%E9%97%AE%E9%A2%98/m-p/1005907#M3121</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;我看在AN2165中有个描述写的是在MPC8260A中“the MPC8260A (HiP4) and revision C of the MPC8260&amp;nbsp;can use these values but require an external multiplexer.”是否MPC8280CVVQLDA型号也是如此？&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Nov 2019 09:24:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8280-SDRAM-60x-Bus%E9%85%8D%E7%BD%AE%E9%97%AE%E9%A2%98/m-p/1005907#M3121</guid>
      <dc:creator>lhb_will</dc:creator>
      <dc:date>2019-11-11T09:24:31Z</dc:date>
    </item>
    <item>
      <title>Re: MPC8280 SDRAM  60x Bus配置问题</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8280-SDRAM-60x-Bus%E9%85%8D%E7%BD%AE%E9%97%AE%E9%A2%98/m-p/1005908#M3122</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Nov 2019 19:50:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8280-SDRAM-60x-Bus%E9%85%8D%E7%BD%AE%E9%97%AE%E9%A2%98/m-p/1005908#M3122</guid>
      <dc:creator>alexander_yakov</dc:creator>
      <dc:date>2019-11-11T19:50:57Z</dc:date>
    </item>
    <item>
      <title>Re: MPC8280 SDRAM  60x Bus配置问题</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8280-SDRAM-60x-Bus%E9%85%8D%E7%BD%AE%E9%97%AE%E9%A2%98/m-p/1005909#M3123</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;如果我使用两块MT48LC4M32B2组成64bit数据，连接到60x BUS上的CS1片选上。B60x_ADD28连接到SDRAM的A0，B60x_ADD27连接到SDRAM的A1...B60x_ADD16连接到SDRAM的A12，其中SDA10连接到SDRAM的A10，BNKSEL连接到SDRAM的BA。PSDMR配置为0xc24b36a3，OR1配置为0xfe002ec0，BR1配置为0xf0000041，SIUMCR配置为0x0e200000。这样是否正确。下面是我的SDRAM初始化序列。&lt;/P&gt;&lt;P&gt;writemmr OR1 0xfe002ec0&lt;BR /&gt;writemmr BR1 0x00000041&lt;/P&gt;&lt;P&gt;writemmr PSRT 0x13&lt;/P&gt;&lt;P&gt;writemmr MPTPR 0x2800&lt;/P&gt;&lt;P&gt;# precharge all banks&lt;BR /&gt;writemmr PSDMR 0x824b36a3&lt;BR /&gt;writemmr PSDMR 0xaa4b36a3&lt;/P&gt;&lt;P&gt;# perform an access&lt;BR /&gt;writemem.b 0x00000000 0x00&lt;/P&gt;&lt;P&gt;# cbr refresh&lt;BR /&gt;writemmr PSDMR 0x8a4b36a3&lt;/P&gt;&lt;P&gt;# perform 8 accesses&lt;BR /&gt;writemem.b 0x00000000 0xFF&lt;BR /&gt;writemem.b 0x00000000 0xFF&lt;BR /&gt;writemem.b 0x00000000 0xFF&lt;BR /&gt;writemem.b 0x00000000 0xFF&lt;BR /&gt;writemem.b 0x00000000 0xFF&lt;BR /&gt;writemem.b 0x00000000 0xFF&lt;BR /&gt;writemem.b 0x00000000 0xFF&lt;BR /&gt;writemem.b 0x00000000 0xFF&lt;/P&gt;&lt;P&gt;; Issue Mode register write&lt;BR /&gt;writemmr PSDMR 0x9a4b36a3&lt;/P&gt;&lt;P&gt;writemem.b 0x00000190 0x00&lt;/P&gt;&lt;P&gt;writemmr PSDMR 0xc24b36a3&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 12 Nov 2019 06:22:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8280-SDRAM-60x-Bus%E9%85%8D%E7%BD%AE%E9%97%AE%E9%A2%98/m-p/1005909#M3123</guid>
      <dc:creator>lhb_will</dc:creator>
      <dc:date>2019-11-12T06:22:12Z</dc:date>
    </item>
  </channel>
</rss>

