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    <title>PowerQUICC ProcessorsのトピックIssue for MPC8245 flash program</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/Issue-for-MPC8245-flash-program/m-p/1000528#M3111</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all, this week I met a very wild issue for MPC8245 board.&amp;nbsp; Now, I can download my program to SDRAM and it works very well, but when I use same ini.tcl to program the elf file to NOR flash, &lt;STRONG&gt;I met the below error:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I added my ini.tcl and connection log to below also, could NXP expert help me?&amp;nbsp; Thanks a lot&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;fl::target -lc "LC for Simple Flash"&lt;BR /&gt;fl::target -b 0x0 0x4b000&lt;BR /&gt;fl::target -v off -l off&lt;BR /&gt;cmdwin::fl::device -d "S29GL064S" -o "4Mx16x2" -a 0xff800000 0x1007fffff&lt;BR /&gt;cmdwin::fl::erase all&lt;BR /&gt; Beginning Operation ... &lt;BR /&gt;------------------------- &lt;BR /&gt;Performing target initialization ... &lt;BR /&gt; Downloading Flash Device Driver ... &lt;BR /&gt; Reading flash ID ...&lt;BR /&gt;Error: Failed reading return status. Can not read target memory at location: 0x000000000000000C.Please make sure that the chip selects are properly configured. &lt;BR /&gt;The CWPP response code is: CCSProtocolPlugin : Error reading memory &lt;BR /&gt;[CCS last error: target is in unexpected RUNNING mode ].&lt;BR /&gt;Error: Getting flash ID failed&lt;BR /&gt;Error: Failed reading return status.Can not read target memory at location: 0x000000000000000C.&lt;BR /&gt;Please make sure that the chip selects are properly configured.&lt;BR /&gt;The CWPP response code is: CCSProtocolPlugin : Error reading memory&lt;BR /&gt;[CCS last error: target is in unexpected RUNNING mode ].&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;the connection log is here:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;ccs_close&lt;BR /&gt; serverh = 0&lt;BR /&gt; ccs_close; ccs_error = 0&lt;BR /&gt;ccs_open&lt;BR /&gt; ipaddr = 127.0.0.1&lt;BR /&gt; port = 41475&lt;BR /&gt; timeout = 15&lt;BR /&gt; serverh = 0&lt;BR /&gt; ccs_open; ccs_error = 0&lt;BR /&gt;ccs_get_connection_count&lt;BR /&gt; serverh = 0&lt;BR /&gt; count = 1&lt;BR /&gt; ccs_get_connection_count; ccs_error = 0&lt;BR /&gt;ccs_available_connections&lt;BR /&gt; serverh = 0&lt;BR /&gt; count = 1&lt;BR /&gt; ccs_available_connections; ccs_error = 0&lt;BR /&gt;ccs_available_connections&lt;BR /&gt; serverh = 0&lt;BR /&gt; count = 1&lt;BR /&gt; ccs_available_connections; ccs_error = 0&lt;BR /&gt;ccs_cc_version&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; version.major = 0&lt;BR /&gt; version.minor = 0&lt;BR /&gt; ccs_cc_version; ccs_error = 0&lt;BR /&gt;ccs_set_timeout&lt;BR /&gt; serverh = 0&lt;BR /&gt; timeout = 15&lt;BR /&gt; ccs_set_timeout; ccs_error = 0&lt;BR /&gt;ccs_available_connections&lt;BR /&gt; serverh = 0&lt;BR /&gt; count = 1&lt;BR /&gt; ccs_available_connections; ccs_error = 0&lt;BR /&gt;ccs_config_server&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; server_config = 0&lt;BR /&gt; value = 12500&lt;BR /&gt; ccs_config_server; ccs_error = 0&lt;BR /&gt;ccs_config_chain&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; device_list: (size = 1)&lt;BR /&gt; device[0]:: core_type=test core(20)&lt;BR /&gt; ccs_config_chain; ccs_error = 0&lt;BR /&gt;ccs_jtag_lock&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; ccs_jtag_lock; ccs_error = 0&lt;BR /&gt;JTAG Diagnostics&lt;/P&gt;&lt;P&gt;Starting Power at Probe test ...&lt;BR /&gt;Test result: PASSED&lt;/P&gt;&lt;P&gt;Starting IR Scan test ...&lt;BR /&gt;Test result: PASSED&lt;/P&gt;&lt;P&gt;Starting Bypass Scan test ...&lt;BR /&gt;Test result: PASSED&lt;/P&gt;&lt;P&gt;Starting Arbitrary TAP State Move test ...&lt;BR /&gt;Test result: PASSED&lt;/P&gt;&lt;P&gt;Detected JTAG IDCODEs: FAILED&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;ccs_jtag_unlock&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; ccs_jtag_unlock; ccs_error = 0&lt;BR /&gt;ccs_config_chain&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; device_list: (size = 1)&lt;BR /&gt; device[0]:: core_type=mpc603e(31)&lt;BR /&gt; ccs_config_chain; ccs_error = 0&lt;BR /&gt;ccs_get_config_chain&lt;BR /&gt; serverh = 0&lt;BR /&gt; device_list: (size = 1)&lt;BR /&gt; ccs_get_config_chain; ccs_error = 0&lt;BR /&gt;ccs_get_config_chain&lt;BR /&gt; serverh = 0&lt;BR /&gt; device_list: (size = 1)&lt;BR /&gt; device[0]:: core_type=mpc603e(31)&lt;BR /&gt; ccs_get_config_chain; ccs_error = 0&lt;BR /&gt;ccs_reset_to_mixed&lt;BR /&gt; chain_pos: (size = 1) { 0 (halt) }&lt;BR /&gt; ccs_reset_to_mixed; ccs_error = 0; duration=405 ms&lt;BR /&gt;ccs_send_message&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; message = 3&lt;BR /&gt; ccs_send_message; ccs_error = 0&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 287&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 80811014&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=3 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; FFF00100&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=1 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2000&lt;BR /&gt; count = 34&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 136)&lt;BR /&gt; 227E227E 00002328 000082A0 00000000&lt;BR /&gt; 00F000F0 24BD4295 00002360 00000000&lt;BR /&gt; FF800100 FF800000 918A4375 00002358&lt;BR /&gt; 00000000 00008270 FFFFFFFF F7FFFFFF&lt;BR /&gt; 24BD4295 3D395017 00000000 B7FFFFFF&lt;BR /&gt; 00000000 FBD67536 00000000 FFFFFFFF&lt;BR /&gt; 00000000 00F000F0 FF800000 FF800000&lt;BR /&gt; FF800000 FFFFFFFF 00000100 00002328&lt;BR /&gt; FFF00100 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=51 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 8&lt;BR /&gt; count = 2&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 8)&lt;BR /&gt; 00000000 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 1&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfff00100]&lt;BR /&gt; data: (size = 256)&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; ccs_read_mem; ccs_error = 0; duration=20 ms&lt;BR /&gt;ccs_read_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfff00200]&lt;BR /&gt; data: (size = 256)&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; ccs_read_mem; ccs_error = 0; duration=20 ms&lt;/P&gt;&lt;P&gt;Executing Initialization File: E:\working\new_git\jg-fmss\04_sw\fmss_app\CFG\fmss_init_CORE.tcl&lt;BR /&gt;thread break: Stopped, 0x0, 0x0, cpuPowerPCBig, Connected (state, tid, pid, cpu, target) &lt;BR /&gt;thread set: Stopped, 0x0, 0x0, cpuPowerPCBig, Connected (state, tid, pid, cpu, target) &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; ccs_stop_core; ccs_error = 0&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt;radix x &lt;BR /&gt; value: (size = 4)&lt;BR /&gt; FFF00100&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfff00100]&lt;BR /&gt;cmdwin::eclipse::config hexprefix 0x &lt;BR /&gt;cmdwin::eclipse::config MemIdentifier v &lt;BR /&gt;cmdwin::eclipse::config MemWidth 32 &lt;BR /&gt;cmdwin::eclipse::config MemAccess 32 &lt;BR /&gt; data: (size = 256)&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; ccs_read_mem; ccs_error = 0; duration=21 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2000&lt;BR /&gt; count = 34&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 136)&lt;BR /&gt; 227E227E 00002328 000082A0 00000000&lt;BR /&gt; 00F000F0 24BD4295 00002360 00000000&lt;BR /&gt; FF800100 FF800000 918A4375 00002358&lt;BR /&gt; 00000000 00008270 FFFFFFFF F7FFFFFF&lt;BR /&gt; 24BD4295 3D395017 00000000 B7FFFFFF&lt;BR /&gt; 00000000 FBD67536 00000000 FFFFFFFF&lt;BR /&gt; 00000000 00F000F0 FF800000 FF800000&lt;BR /&gt; FF800000 FFFFFFFF 00000100 00002328&lt;BR /&gt; FFF00100 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=51 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 8&lt;BR /&gt; count = 2&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 8)&lt;BR /&gt; 00000000 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 1&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;thread break: Stopped, 0x0, 0x0, cpuPowerPCBig, Connected (state, tid, pid, cpu, target) &lt;BR /&gt;cmdwin::eclipse::config MemSwap off &lt;BR /&gt;cmdwin::stop &lt;BR /&gt;cmdwin::wait 0x200 &lt;BR /&gt;cmdwin::reset &lt;BR /&gt;ccs_reset_to_mixed&lt;BR /&gt; chain_pos: (size = 1) { 0 (halt) }&lt;BR /&gt; ccs_reset_to_mixed; ccs_error = 0; duration=405 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; FFF00100&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; FFF00100&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=1 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x04000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 04000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 16bit = 0x600 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:2;address:0xfee00000]&lt;BR /&gt; data: (size = 2)&lt;BR /&gt; 0600&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x80000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 80000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=3 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x84000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 84000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00000000 &lt;BR /&gt; ccs_stop_core; ccs_error = 0&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; FFF00100&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=1 ms&lt;BR /&gt;ccs_read_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfff00100]&lt;BR /&gt; data: (size = 256)&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; ccs_read_mem; ccs_error = 0; duration=20 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=1 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2000&lt;BR /&gt; count = 34&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 136)&lt;BR /&gt; 227E227E 00002328 000082A0 00000000&lt;BR /&gt; 00F000F0 24BD4295 00002360 00000000&lt;BR /&gt; FF800100 FF800000 918A4375 00002358&lt;BR /&gt; 00000000 00008270 FFFFFFFF F7FFFFFF&lt;BR /&gt; 24BD4295 3D395017 00000000 B7FFFFFF&lt;BR /&gt; 00000000 FBD67536 00000000 FFFFFFFF&lt;BR /&gt; 00000000 00F000F0 FF800000 FF800000&lt;BR /&gt; FF800000 FFFFFFFF 00000100 00002328&lt;BR /&gt; FFF00100 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=51 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 8&lt;BR /&gt; count = 2&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 8)&lt;BR /&gt; 00000000 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 1&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;thread break: Stopped, 0x0, 0x0, cpuPowerPCBig, Connected (state, tid, pid, cpu, target) &lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x88000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 88000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x8C000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 8C000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=3 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x90000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 90000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0xFF000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; FF000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x94000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 94000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x98000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 98000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x07000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 07000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x9C000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 9C000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xA0000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; A0000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x01000032 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 01000032&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xA8000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; A8000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x981A14FF &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 981A14FF&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xAC000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; AC000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x0C060C00 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 0C060C00&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x78000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 78000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x000000FC &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 000000FC&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xB8000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; B8000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 8bit = 0x0 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:1;address:0xfee00000]&lt;BR /&gt; data: (size = 1)&lt;BR /&gt; 00&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=3 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xF4000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; F4000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0xCC044004 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; CC044004&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xF8000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; F8000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00004078 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00004078&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xFC000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; FC000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x39323235 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 39323235&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xF0000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; F0000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x0200E875 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 0200E875&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x72000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 72000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00002 8bit = 0xE0 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:1;address:0xfee00002]&lt;BR /&gt; data: (size = 1)&lt;BR /&gt; E0&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x73000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 73000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00003 8bit = 0xD1 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:1;address:0xfee00003]&lt;BR /&gt; data: (size = 1)&lt;BR /&gt; D1&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=1 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x74000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 74000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=3 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00002 16bit = 0x00FD &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:2;address:0xfee00002]&lt;BR /&gt; data: (size = 2)&lt;BR /&gt; 00FD&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=3 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x76000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 76000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00002 8bit = 0x40 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:1;address:0xfee00002]&lt;BR /&gt; data: (size = 1)&lt;BR /&gt; 40&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xA3000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; A3000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00003 8bit = 0x32 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:1;address:0xfee00003]&lt;BR /&gt; data: (size = 1)&lt;BR /&gt; 32&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::reg MSR = 0x00001002 &lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2034&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00001002&lt;BR /&gt; ccs_write_register; ccs_error = 0; duration=1 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2034&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00001002&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0x700 = 0x48000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x00000700]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 48000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::reg IABR = 0x702 &lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 1010&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000702&lt;BR /&gt; ccs_write_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 1010&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000702&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::reg SP = 0xF &lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2001&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 0000000F&lt;BR /&gt; ccs_write_register; ccs_error = 0; duration=3 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2001&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 0000000F&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=3 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2000&lt;BR /&gt; count = 34&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 136)&lt;BR /&gt; 227E227E 0000000F 000082A0 00000000&lt;BR /&gt; 00F000F0 24BD4295 00002360 00000000&lt;BR /&gt; FF800100 FF800000 918A4375 00002358&lt;BR /&gt; 00000000 00008270 FFFFFFFF F7FFFFFF&lt;BR /&gt; 24BD4295 3D395017 00000000 B7FFFFFF&lt;BR /&gt; 00000000 FBD67536 00000000 FFFFFFFF&lt;BR /&gt; 00000000 00F000F0 FF800000 FF800000&lt;BR /&gt; FF800000 FFFFFFFF 00000100 00002328&lt;BR /&gt; FFF00100 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=52 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 8&lt;BR /&gt; count = 2&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 8)&lt;BR /&gt; 00000000 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=1 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 1&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=1 ms&lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; ccs_stop_core; ccs_error = 0&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x00000000]&lt;BR /&gt; data: (size = 640)&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 000000FF 000000FF 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; FFFFFFFE 00000000 00000000 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=29 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x000002b0]&lt;BR /&gt; data: (size = 176)&lt;BR /&gt; 00002AF0 00000000 00002B38 00000000&lt;BR /&gt; 38380000 00000000 10080000 00000000&lt;BR /&gt; 10080000 00000000 20080000 00000000&lt;BR /&gt; 28180000 00000000 10080000 00000000&lt;BR /&gt; 00002360 000002A4 000002C0 00002618&lt;BR /&gt; 00000074 000002C8 0000268C 000000C4&lt;BR /&gt; 000002D0 00002750 000000CC 000002D8&lt;BR /&gt; 0000281C 000001C4 000002E0 000029E0&lt;BR /&gt; 00000024 000002E8 00000338 000002F0&lt;BR /&gt; 00002A04 00002360 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=9 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x00002360]&lt;BR /&gt; data: (size = 3680)&lt;BR /&gt; 9421FFD0 7C0802A6 90010034 39610030&lt;BR /&gt; 4800070D 7C000026 90010010 7C3F0B78&lt;BR /&gt; 3F80FF80 7F9BE378 3BC00000 3BC00000&lt;BR /&gt; 48000018 57DA063E 3F2DFFFF 3B397EF8&lt;BR /&gt; 7F59F1AE 3BDE0001 2E1E0100 4190FFE8&lt;BR /&gt; 3F40FF80 3F2DFFFF 3B397D90 93590004&lt;BR /&gt; 3F2DFFFF 3B397D90 83390000 2E190003&lt;BR /&gt; 419200D0 4090001C 2E190001 41920034&lt;BR /&gt; 409000A4 2E190000 40900018 480001AC&lt;BR /&gt; 2E190005 41920124 409001A0 480000D0&lt;BR /&gt; 3C6DFFFF 38637D90 48000211 480001AC&lt;BR /&gt; 3BA00000 48000048 3800FFFF 3C6DFFFF&lt;BR /&gt; 38637D90 9003000C 3C6DFFFF 38637D90&lt;BR /&gt; 7FA4EB78 48000259 3F2DFFFF 3B397D90&lt;BR /&gt; 9079000C 3F2DFFFF 3B397D90 8339000C&lt;BR /&gt; 2E190000 4092001C 3BBD0001 3F2DFFFF&lt;BR /&gt; 3B397D90 83390008 7E1DC840 4190FFAC&lt;BR /&gt; 3B400000 3F2DFFFF 3B397D90 93590008&lt;BR /&gt; 48000138 3C6DFFFF 38637D90 480002C5&lt;BR /&gt; 3F2DFFFF 3B397D90 9079000C 4800011C&lt;BR /&gt; 3C6DFFFF 38637D90 48000375 3F4DFFFF&lt;BR /&gt; 3B5A7D90 907A000C 3B200000 3F4DFFFF&lt;BR /&gt; 3B5A7D90 933A0008 480000F0 3C6DFFFF&lt;BR /&gt; 38637D90 389F0008 3CADFFFF 38A57E80&lt;BR /&gt; 48000501 3F4DFFFF 3B5A7D90 907A000C&lt;BR /&gt; 833F0008 3F4DFFFF 3B5A7D90 933A0008&lt;BR /&gt; 3F2DFFFF 3B397E80 3F4DFFFF 3B5A7D90&lt;BR /&gt; 933A0010 480000A4 3C6DFFFF 38637D90&lt;BR /&gt; 480002FD 3F2DFFFF 3B397D90 9079000C&lt;BR /&gt; 3F2DFFFF 3B397D90 8339000C 2E190000&lt;BR /&gt; 40920044 3C6DFFFF 38637D90 389F0008&lt;BR /&gt; 3CADFFFF 38A57E80 48000489 833F0008&lt;BR /&gt; 3F4DFFFF 3B5A7D90 933A0008 3F2DFFFF&lt;BR /&gt; 3B397E80 3F4DFFFF 3B5A7D90 933A0010&lt;BR /&gt; 48000038 3B400000 3F2DFFFF 3B397D90&lt;BR /&gt; 93590008 48000024 3B200200 3F4DFFFF&lt;BR /&gt; 3B5A7D90 933A000C 3B200000 3F4DFFFF&lt;BR /&gt; 3B5A7D90 933A0008 3F2000F0 3B3900F0&lt;BR /&gt; 3F4DFFFF 3B5A7D90 835A0004 933A0400&lt;BR /&gt; 7FE00008 48000031 4BFFFDE8 7FEAFB78&lt;BR /&gt; 818A0010 7D8FF120 396A0030 480004E1&lt;BR /&gt; 81410000 800A0004 7D415378 7C0803A6&lt;BR /&gt; 4E800020 00000000 9421FFF0 38210010&lt;BR /&gt; 4E800020 00454E44 9421FFF0 93E1000C&lt;BR /&gt; 93C10008 83E30004 3BC00000 3C8000F0&lt;BR /&gt; 388400F0 909F0000 3C8000AA 388400AA&lt;BR /&gt; 909F1554 3C800055 38840055 909F0AA8&lt;BR /&gt; 3C800090 38840090 909F1554 801F0000&lt;BR /&gt; 900D8014 801F0004 900D8010 3C8000F0&lt;BR /&gt; 388400F0 909F0000 7FC3F378 83E1000C&lt;BR /&gt; 83C10008 38210010 4E800020 9421FFE0&lt;BR /&gt; 93E1001C 93C10018 80A30010 5480103A&lt;BR /&gt; 7FE5002E 3BC00000 3CA00001 38A5F0F0&lt;BR /&gt; B0BF0000 3CA00001 38A59090 B0BF0000&lt;BR /&gt; A01F0004 2C000000 4182000C 38600000&lt;BR /&gt; 48000070 3CA00001 38A5F0F0 B0BF0000&lt;BR /&gt; 380000AA B01F0AAA 38000055 B01F0554&lt;BR /&gt; 38000080 B01F0AAA 380000AA B01F0AAA&lt;BR /&gt; 38000055 B01F0554 38000030 B01F0000&lt;BR /&gt; A01F0000 B0010008 4800000C A01F0000&lt;BR /&gt; B0010008 A0010008 54000630 2C000080&lt;BR /&gt; 4082FFEC 380000F0 B01F0000 7FC3F378&lt;BR /&gt; 83E1001C 83C10018 38210020 4E800020&lt;BR /&gt; 9421FFE0 93E1001C 93C10018 93A10014&lt;BR /&gt; 93810010 38000000 90010008 3BC00000&lt;BR /&gt; 3BA00080 3B800080 83E30004 3C80F0F1&lt;BR /&gt; 3884F0F0 909F0000 3C8000AA 388400AA&lt;BR /&gt; 909F1554 3C800055 38840055 909F0AA8&lt;BR /&gt; 3C800080 38840080 909F1554 3C8000AA&lt;BR /&gt; 388400AA 909F1554 3C800055 38840055&lt;BR /&gt; 909F0AA8 3C800010 38840010 909F1554&lt;BR /&gt; 3C800070 38840070 909F1554 5785043E&lt;BR /&gt; 809F0000 57A0043E 7C800038 7C050040&lt;BR /&gt; 4082FFEC 3C80F0F1 3884F0F0 909F0000&lt;BR /&gt; 7FC3F378 83E1001C 83C10018 83A10014&lt;BR /&gt; 83810010 38210020 4E800020 9421FFC0&lt;BR /&gt; 7C0802A6 90010044 39610040 48000259&lt;BR /&gt; 7C3F0B78 7C7B1B78 38000000 901F001C&lt;BR /&gt; 38000080 B01F000A 38000080 B01F0008&lt;BR /&gt; 83DB0004 57C00024 901F0018 83BB0010&lt;BR /&gt; 801B0008 901F0014 801F0014 5400F87E&lt;BR /&gt; 901F0010 3C600001 3863F0F0 907E0000&lt;BR /&gt; 3C600001 38639090 907E0000 3C600001&lt;BR /&gt; 3863F0F0 907E0000 38000098 807F0018&lt;BR /&gt; B00300AA 380000F0 807F0018 B0030000&lt;BR /&gt; 3C600001 3863F0F0 907E0000 3C600001&lt;BR /&gt; 38639090 907E0000 801F0014 540007FE&lt;BR /&gt; 2C000000 41820030 801F0014 7C1D0214&lt;BR /&gt; 901F000C 380000FF 807F000C 98030000&lt;BR /&gt; 38030001 901F000C 807F0010 38030001&lt;BR /&gt; 901F0010 3C600001 3863F0F0 907E0000&lt;BR /&gt; 38000000 901F0020 4800007C 57DC0024&lt;BR /&gt; 380000AA B01C0AAA 38000055 B01C0554&lt;BR /&gt; 380000A0 B01C0AAA A01D0000 901E0000&lt;BR /&gt; A01F000A 54000630 B01F000A A01D0000&lt;BR /&gt; 54000630 5400043E B01F0008 A01F0008&lt;BR /&gt; 54000630 B01F0008 A09F0008 807E0000&lt;BR /&gt; A01F000A 7C600038 7C040040 4082FFEC&lt;BR /&gt; 3BDE0004 3BBD0002 807F0020 38030001&lt;BR /&gt; 901F0020 807F0020 801F0010 7C030040&lt;BR /&gt; 40800010 801F001C 2C000000 4182FF70&lt;BR /&gt; 3BDEFFFC 380000F0 901E0000 807F001C&lt;BR /&gt; 7FEAFB78 396A0040 4800010D 81410000&lt;BR /&gt; 800A0004 7D415378 7C0803A6 4E800020&lt;BR /&gt; 9421FFF0 93E1000C 93C10008 3BE00000&lt;BR /&gt; 83C30004 83E1000C 83C10008 38210010&lt;BR /&gt; 4E800020 00000000 9421FFF0 7C0802A6&lt;BR /&gt; 90010014 48000020 80030000 3880FFFF&lt;BR /&gt; 900D8018 81830004 80630008 7D8903A6&lt;BR /&gt; 4E800421 806D8018 2C030000 4082FFDC&lt;BR /&gt; 80010014 7C0803A6 38210010 4E800020&lt;BR /&gt; 91CBFFB8 91EBFFBC 920BFFC0 922BFFC4&lt;BR /&gt; 924BFFC8 926BFFCC 928BFFD0 92ABFFD4&lt;BR /&gt; 92CBFFD8 92EBFFDC 930BFFE0 932BFFE4&lt;BR /&gt; 934BFFE8 936BFFEC 938BFFF0 93ABFFF4&lt;BR /&gt; 93CBFFF8 93EBFFFC 4E800020 00000000&lt;BR /&gt; 81CBFFB8 81EBFFBC 820BFFC0 822BFFC4&lt;BR /&gt; 824BFFC8 826BFFCC 828BFFD0 82ABFFD4&lt;BR /&gt; 82CBFFD8 82EBFFDC 830BFFE0 832BFFE4&lt;BR /&gt; 834BFFE8 836BFFEC 838BFFF0 83ABFFF4&lt;BR /&gt; 83CBFFF8 83EBFFFC 4E800020 00000000&lt;BR /&gt; 9421FFF0 7C0802A6 90010014 800D8000&lt;BR /&gt; 2C00FFFE 40820020 38610008 3881000C&lt;BR /&gt; 480003C5 80610008 8081000C 48000055&lt;BR /&gt; 906D8000 80010014 7C0803A6 38210010&lt;BR /&gt; 4E800020 00000000 9421FFF0 7C0802A6&lt;BR /&gt; 90010014 806D8000 2C03FFFE 41820010&lt;BR /&gt; 48000059 3800FFFE 900D8000 80010014&lt;BR /&gt; 7C0803A6 38210010 4E800020 00000000&lt;BR /&gt; 3CAD0000 38A58030 80050008 2C000000&lt;BR /&gt; 4082001C 90650000 38000001 38600000&lt;BR /&gt; 90850004 90050008 4E800020 3860FFFF&lt;BR /&gt; 4E800020 00000000 2C030000 4C820020&lt;BR /&gt; 1C03000C 3C6D0000 38638030 7C630214&lt;BR /&gt; 38000000 90030000 90030004 90030008&lt;BR /&gt; 4E800020 00000000 9421FFF0 7C0802A6&lt;BR /&gt; 90010014 4BFFFE25 818D8020 2C0C0000&lt;BR /&gt; 41820014 7D8903A6 4E800421 38000000&lt;BR /&gt; 900D8020 818D8024 2C0C0000 41820014&lt;BR /&gt; 7D8903A6 4E800421 38000000 900D8024&lt;BR /&gt; 4BFFF9F5 80010014 7C0803A6 38210010&lt;BR /&gt; 4E800020 4E800020 3CA0FFFF 60A5FFF1&lt;BR /&gt; 7CA51838 7C651850 7C841A14 7C0004AC&lt;BR /&gt; 30A50008 3484FFF8 4080FFF4 4C00012C&lt;BR /&gt; 4E800020 3C600001 38638270 7C636850&lt;BR /&gt; 4E800020 7C0802A6 4BFFFFED 28030000&lt;BR /&gt; 41820044 3CA20000 3C820000 38A5AEE0&lt;BR /&gt; 3884AF18 7CC52050 28060000 41820028&lt;BR /&gt; 54C6F0BE 7CC903A6 38A5FFFC 84C50004&lt;BR /&gt; 7CC61A14 80E60000 7CE71A14 90E60000&lt;BR /&gt; 4200FFEC 7C0803A6 4E800020 7C0802A6&lt;BR /&gt; 3DA00001 39AD8270 3C400001 384282A0&lt;BR /&gt; 429F0005 7C8802A6 3C620000 3863AA44&lt;BR /&gt; 7C632050 28030000 4182000C 7DAD1A14&lt;BR /&gt; 7C421A14 3C2D0000 3821A0F0 7C0803A6&lt;BR /&gt; 4E800020 9421FFD0 7C0802A6 90010034&lt;BR /&gt; 39610030 4BFFFD69 4BFFFF3D 9061001C&lt;BR /&gt; 3C620000 3BE3AE78 801F0000 2C000000&lt;BR /&gt; 4082001C 801F0008 2C000000 40820010&lt;BR /&gt; 801F000C 2C000000 418200D0 807F0004&lt;BR /&gt; 801F0000 7C001810 7C000110 7C0000D0&lt;BR /&gt; 90010008 80010008 2C000000 41820028&lt;BR /&gt; 807F0004 8001001C 7C030214 90010010&lt;BR /&gt; 807F0000 8001001C 7C030214 9001000C&lt;BR /&gt; 48000014 801F0000 90010010 801F0004&lt;BR /&gt; 9001000C 807F000C 801F0008 7C001810&lt;BR /&gt; 7C000110 7C0000D0 90010008 80010008&lt;BR /&gt; 2C000000 41820024 807F000C 8001001C&lt;BR /&gt; 7FA30214 807F0008 8001001C 7C030214&lt;BR /&gt; 90010014 48000010 83BF0008 801F000C&lt;BR /&gt; 90010014 80010014 7C1D0050 90010018&lt;BR /&gt; 7FA3EB78 80810010 80A10018 4800014D&lt;BR /&gt; 3BFF0010 4BFFFF14 3C620000 3BC3AEC8&lt;BR /&gt; 801E0000 2C000000 40820010 801E0004&lt;BR /&gt; 2C000000 41820074 807E0004 801E0000&lt;BR /&gt; 7C001810 7C000110 7C0000D0 90010008&lt;BR /&gt; 80010008 2C000000 41820024 807E0004&lt;BR /&gt; 8001001C 7FA30214 807E0000 8001001C&lt;BR /&gt; 7C030214 90010014 48000010 83BE0000&lt;BR /&gt; 801E0004 90010014 80010014 7C1D0050&lt;BR /&gt; 90010018 7FA3EB78 80810018 48000115&lt;BR /&gt; 3BDE0008 4BFFFF7C 4BFFFDBD 39610030&lt;BR /&gt; 4BFFFC1D 80010034 7C0803A6 38210030&lt;BR /&gt; 4E800020 9421FFF0 93E1000C 7C5F1378&lt;BR /&gt; 93E40000 3CA20000 38058098 90030000&lt;BR /&gt; 83E1000C 38210010 4E800020 00000000&lt;BR /&gt; 7C6E1B78 7C8F2378 7CB02B78 4BFFFD29&lt;BR /&gt; 4BFFFDBD 9421FFF8 38000000 90010000&lt;BR /&gt; 3800FFFF 90010004 4BFFFDED 3C620000&lt;BR /&gt; 3863A368 7C6803A6 4E800021 3CC20000&lt;BR /&gt; 38C6A0C0 7CC803A6 7DC37378 7DE47B78&lt;BR /&gt; 7E058378 4E800021 3CC20000 38C6A938&lt;BR /&gt; 7CC803A6 4E800021 9421FFF0 7C0802A6&lt;BR /&gt; 2C050000 90010014 93E1000C 7CBF2B78&lt;BR /&gt; 93C10008 7C7E1B78 4182001C 7C032040&lt;BR /&gt; 41820014 48000045 7FC3F378 7FE4FB78&lt;BR /&gt; 4BFFFC99 80010014 83E1000C 83C10008&lt;BR /&gt; 7C0803A6 38210010 4E800020 00000000&lt;BR /&gt; 2C040000 4D820020 7C852378 38800000&lt;BR /&gt; 48000118 4E800020 7C041840 41800028&lt;BR /&gt; 3884FFFF 38C3FFFF 38A50001 4800000C&lt;BR /&gt; 8C040001 9C060001 34A5FFFF 4082FFF4&lt;BR /&gt; 4E800020 7C842A14 7CC32A14 38A50001&lt;BR /&gt; 48000010 60000000 8C04FFFF 9C06FFFF&lt;BR /&gt; 34A5FFFF 4082FFF4 4E800020 00000000&lt;BR /&gt; 28050020 5487063E 38C3FFFF 41800090&lt;BR /&gt; 7CC030F8 540007BF 41820014 7CA02850&lt;BR /&gt; 3400FFFF 9CE60001 4082FFF8 2C070000&lt;BR /&gt; 4182001C 54E4402E 54E3C00E 54E0801E&lt;BR /&gt; 7CE42378 7C600378 7C870378 54A0D97F&lt;BR /&gt; 3866FFFD 4182002C 90E30004 3400FFFF&lt;BR /&gt; 90E30008 90E3000C 90E30010 90E30014&lt;BR /&gt; 90E30018 90E3001C 94E30020 4082FFDC&lt;BR /&gt; 54A0F77F 41820010 3400FFFF 94E30004&lt;BR /&gt; 4082FFF8 38C30003 54A507BE 2C050000&lt;BR /&gt; 4D820020 60000000 34A5FFFF 9CE60001&lt;BR /&gt; 4082FFF8 4E800020 9421FFF0 7C0802A6&lt;BR /&gt; 90010014 93E1000C 7C7F1B78 4BFFFF35&lt;BR /&gt; 7FE3FB78 83E1000C 80010014 7C0803A6&lt;BR /&gt; 38210010 4E800020 00000270 00000000&lt;BR /&gt; 00000270 00000000 00000280 00000270&lt;BR /&gt; 00000280 00000270 00000360 000002B0&lt;BR /&gt; 00000360 000002B0 000031C0 00002360&lt;BR /&gt; 000031C0 00002360 00000000 00000000&lt;BR /&gt; 00000000 00000000 000002A0 00000280&lt;BR /&gt; 000002B0 000002A0 00000000 00000000&lt;BR /&gt; 000002F0 000002F8 000002FC 00000304&lt;BR /&gt; 00000308 00000310 00000314 0000031C&lt;BR /&gt; 00000320 00000328 0000032C 00000334&lt;BR /&gt; 000002B0 000002B8 00000000 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=157 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x00000000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x00000010]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 000031C0&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x00000004]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; FF800000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x0000000c]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2013&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_register; ccs_error = 0; duration=3 ms&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00002F00&lt;BR /&gt; ccs_write_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00002F00&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_run_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; ccs_run_core; ccs_error = 0&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000700&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x0000000c]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 15420000&lt;BR /&gt; ccs_read_mem; ccs_error = -2147483639; duration=2 ms&lt;BR /&gt; Error message: target is in unexpected RUNNING mode&lt;BR /&gt;ccs_get_messages&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; message: (size = 0)&lt;BR /&gt; ccs_get_messages; ccs_error = 0&lt;BR /&gt;ccs_close&lt;BR /&gt; serverh = 0&lt;BR /&gt; ccs_close; ccs_error = 0&lt;BR /&gt;ccs_core_run_mode&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; mode = 57996680&lt;BR /&gt; ccs_core_run_mode; ccs_error = 7&lt;BR /&gt; Error message: Invalid handle&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;My ini.tcl file is here:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;proc init_fmss_cpu {} {&lt;BR /&gt; &lt;BR /&gt; variable SSPR "Standard Special Purpose Registers/" &lt;BR /&gt; &lt;BR /&gt; global IMMRBase&lt;BR /&gt; &lt;BR /&gt; # Set the IMMR so the debugger plugin knows where it is since&lt;BR /&gt; # the IMMR itself is a memory mapped register. This does not&lt;BR /&gt; # actually write anything to the target, it is simply to inform&lt;BR /&gt; # the debugger plugin where the IMMR is&lt;/P&gt;&lt;P&gt;#eppc::setMMRBase $IMMRBase&lt;/P&gt;&lt;P&gt;# relocate internal memory space&lt;BR /&gt; # IMMR&lt;BR /&gt;#mem [IMMR 0x101A8] = 0x04700000 &lt;BR /&gt; &lt;BR /&gt;#set IMMRBase 0x04700000&lt;BR /&gt;#eppc::setMMRBase $IMMRBase&lt;/P&gt;&lt;P&gt;# Main System Clock Configuration Registers &lt;BR /&gt; # Machine Mode Register&lt;BR /&gt;#reg ${SSPR}MSR = 0x1002&lt;/P&gt;&lt;P&gt;# PDTEM&lt;BR /&gt;#mem [IMMR 0x10054] 8bit = 0x00 &lt;BR /&gt; # RMR &lt;BR /&gt;#mem [IMMR 0x10C94] 16bit = 0x0001&lt;/P&gt;&lt;P&gt;# Setup the chip selects&lt;/P&gt;&lt;P&gt;#mem v:0x00000000 8bit = 0xFF&lt;BR /&gt; #CBR refresh.&lt;BR /&gt; &lt;BR /&gt; mem v:0xFEC00000 = 0x04000080&lt;BR /&gt; mem v:0xFEE00000 16bit = 0x600; # bus master and responds to pci memory&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0x80000080; # starting_address_1&lt;BR /&gt; mem v:0xFEE00000 = 0x00000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x84000080; # starting_address_2&lt;BR /&gt; mem v:0xFEE00000 = 0x00000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x88000080; # extended_starting_address_1&lt;BR /&gt; mem v:0xFEE00000 = 0x00000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x8C000080; # extended_starting_address_2&lt;BR /&gt; mem v:0xFEE00000 = 0x00000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x90000080; # mem_ending_address_1&lt;BR /&gt; mem v:0xFEE00000 = 0xFF000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x94000080; # mem_ending_address_2&lt;BR /&gt; mem v:0xFEE00000 = 0x00000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x98000080; # extended_mem_ending_address_1&lt;BR /&gt; mem v:0xFEE00000 = 0x07000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x9C000080; # extended_mem_ending_address_2&lt;BR /&gt; mem v:0xFEE00000 = 0x00000000;&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0xA0000080; # bank 0 enable&lt;BR /&gt; mem v:0xFEE00000 = 0x01000032;&lt;BR /&gt; &lt;BR /&gt; mem v:0xFEC00000 = 0xA8000080; # PICR_1&lt;BR /&gt; #mem v:0xFEE00000 = 0x901A1400; # map B, flash write, processor parked on the data bus&lt;BR /&gt; mem v:0xFEE00000 = 0x981A14FF; # map B, flash write, processor parked on the data bus&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0xAC000080; # PICR_2&lt;BR /&gt; mem v:0xFEE00000 = 0x0C060C00; # ROM/Flash WR lockout disable&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0x78000080; # EUMBBAR&lt;BR /&gt; mem v:0xFEE00000 = 0x000000FC; # 0xFC000000&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0xB8000080; # ECC error&lt;BR /&gt; mem v:0xFEE00000 8bit = 0x0;&lt;BR /&gt; &lt;BR /&gt;# ----- Enable memory, 8-bit data path for ROM back 0, enable refresh&lt;BR /&gt;# ----- during sleep, RAM type = SDRAM, 11 or 12 row bits&lt;BR /&gt; mem v:0xFEC00000 = 0xF4000080; # MCCR_2&lt;BR /&gt; mem v:0xFEE00000 = 0xCC044004;&lt;BR /&gt; mem v:0xFEC00000 = 0xF8000080; # MCCR_3&lt;BR /&gt; mem v:0xFEE00000 = 0x00004078;&lt;BR /&gt; mem v:0xFEC00000 = 0xFC000080; # MCCR_4&lt;BR /&gt; mem v:0xFEE00000 = 0x39323235;&lt;BR /&gt; mem v:0xFEC00000 = 0xF0000080; # MCCR_1&lt;BR /&gt; mem v:0xFEE00000 = 0x0200E875;&lt;BR /&gt; &lt;BR /&gt; mem v:0xFEC00000 = 0x72000080; # PMCR_2&lt;BR /&gt; mem v:0xFEE00002 8bit = 0xE0; # refresh sdram during sleep&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0x73000080; # ODCR&lt;BR /&gt; mem v:0xFEE00003 8bit = 0xD1;&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0x74000080; # CDCR&lt;BR /&gt; mem v:0xFEE00002 16bit = 0x00FD;&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0x76000080; # MDCR&lt;BR /&gt; mem v:0xFEE00002 8bit = 0x40;&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0xA3000080; # PGMAX&lt;BR /&gt; mem v:0xFEE00003 8bit = 0x32;&lt;/P&gt;&lt;P&gt;reg MSR = 0x00001002; # machine check exceptions enable, Vector=0x000n_nnnn&lt;/P&gt;&lt;P&gt;#;valid opcode at program exception&lt;BR /&gt; mem v:0x700 = 0x48000000;&lt;/P&gt;&lt;P&gt;# breakpoint at 0x700 - necessary for flash programmer&lt;BR /&gt; reg IABR = 0x702; # 0x700 is addr, 2 is enable&lt;/P&gt;&lt;P&gt;reg SP = 0xF; # prevent stack walk&lt;BR /&gt; &lt;BR /&gt; # perform 8 accesses&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;proc envsetup {} {&lt;BR /&gt; # Environment Setup&lt;BR /&gt; radix x &lt;BR /&gt; config hexprefix 0x&lt;BR /&gt; config MemIdentifier v&lt;BR /&gt; config MemWidth 32 &lt;BR /&gt; config MemAccess 32 &lt;BR /&gt; config MemSwap off&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;#-------------------------------------------------------------------------------&lt;BR /&gt;# Main &lt;BR /&gt;#-------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;envsetup&lt;BR /&gt; &lt;BR /&gt; stop&lt;BR /&gt; wait 0x200&lt;BR /&gt; reset&lt;/P&gt;&lt;P&gt;init_fmss_cpu&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 23 Mar 2020 05:57:36 GMT</pubDate>
    <dc:creator>gang_liu</dc:creator>
    <dc:date>2020-03-23T05:57:36Z</dc:date>
    <item>
      <title>Issue for MPC8245 flash program</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Issue-for-MPC8245-flash-program/m-p/1000528#M3111</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all, this week I met a very wild issue for MPC8245 board.&amp;nbsp; Now, I can download my program to SDRAM and it works very well, but when I use same ini.tcl to program the elf file to NOR flash, &lt;STRONG&gt;I met the below error:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I added my ini.tcl and connection log to below also, could NXP expert help me?&amp;nbsp; Thanks a lot&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;fl::target -lc "LC for Simple Flash"&lt;BR /&gt;fl::target -b 0x0 0x4b000&lt;BR /&gt;fl::target -v off -l off&lt;BR /&gt;cmdwin::fl::device -d "S29GL064S" -o "4Mx16x2" -a 0xff800000 0x1007fffff&lt;BR /&gt;cmdwin::fl::erase all&lt;BR /&gt; Beginning Operation ... &lt;BR /&gt;------------------------- &lt;BR /&gt;Performing target initialization ... &lt;BR /&gt; Downloading Flash Device Driver ... &lt;BR /&gt; Reading flash ID ...&lt;BR /&gt;Error: Failed reading return status. Can not read target memory at location: 0x000000000000000C.Please make sure that the chip selects are properly configured. &lt;BR /&gt;The CWPP response code is: CCSProtocolPlugin : Error reading memory &lt;BR /&gt;[CCS last error: target is in unexpected RUNNING mode ].&lt;BR /&gt;Error: Getting flash ID failed&lt;BR /&gt;Error: Failed reading return status.Can not read target memory at location: 0x000000000000000C.&lt;BR /&gt;Please make sure that the chip selects are properly configured.&lt;BR /&gt;The CWPP response code is: CCSProtocolPlugin : Error reading memory&lt;BR /&gt;[CCS last error: target is in unexpected RUNNING mode ].&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;the connection log is here:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;ccs_close&lt;BR /&gt; serverh = 0&lt;BR /&gt; ccs_close; ccs_error = 0&lt;BR /&gt;ccs_open&lt;BR /&gt; ipaddr = 127.0.0.1&lt;BR /&gt; port = 41475&lt;BR /&gt; timeout = 15&lt;BR /&gt; serverh = 0&lt;BR /&gt; ccs_open; ccs_error = 0&lt;BR /&gt;ccs_get_connection_count&lt;BR /&gt; serverh = 0&lt;BR /&gt; count = 1&lt;BR /&gt; ccs_get_connection_count; ccs_error = 0&lt;BR /&gt;ccs_available_connections&lt;BR /&gt; serverh = 0&lt;BR /&gt; count = 1&lt;BR /&gt; ccs_available_connections; ccs_error = 0&lt;BR /&gt;ccs_available_connections&lt;BR /&gt; serverh = 0&lt;BR /&gt; count = 1&lt;BR /&gt; ccs_available_connections; ccs_error = 0&lt;BR /&gt;ccs_cc_version&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; version.major = 0&lt;BR /&gt; version.minor = 0&lt;BR /&gt; ccs_cc_version; ccs_error = 0&lt;BR /&gt;ccs_set_timeout&lt;BR /&gt; serverh = 0&lt;BR /&gt; timeout = 15&lt;BR /&gt; ccs_set_timeout; ccs_error = 0&lt;BR /&gt;ccs_available_connections&lt;BR /&gt; serverh = 0&lt;BR /&gt; count = 1&lt;BR /&gt; ccs_available_connections; ccs_error = 0&lt;BR /&gt;ccs_config_server&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; server_config = 0&lt;BR /&gt; value = 12500&lt;BR /&gt; ccs_config_server; ccs_error = 0&lt;BR /&gt;ccs_config_chain&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; device_list: (size = 1)&lt;BR /&gt; device[0]:: core_type=test core(20)&lt;BR /&gt; ccs_config_chain; ccs_error = 0&lt;BR /&gt;ccs_jtag_lock&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; ccs_jtag_lock; ccs_error = 0&lt;BR /&gt;JTAG Diagnostics&lt;/P&gt;&lt;P&gt;Starting Power at Probe test ...&lt;BR /&gt;Test result: PASSED&lt;/P&gt;&lt;P&gt;Starting IR Scan test ...&lt;BR /&gt;Test result: PASSED&lt;/P&gt;&lt;P&gt;Starting Bypass Scan test ...&lt;BR /&gt;Test result: PASSED&lt;/P&gt;&lt;P&gt;Starting Arbitrary TAP State Move test ...&lt;BR /&gt;Test result: PASSED&lt;/P&gt;&lt;P&gt;Detected JTAG IDCODEs: FAILED&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;ccs_jtag_unlock&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; ccs_jtag_unlock; ccs_error = 0&lt;BR /&gt;ccs_config_chain&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; device_list: (size = 1)&lt;BR /&gt; device[0]:: core_type=mpc603e(31)&lt;BR /&gt; ccs_config_chain; ccs_error = 0&lt;BR /&gt;ccs_get_config_chain&lt;BR /&gt; serverh = 0&lt;BR /&gt; device_list: (size = 1)&lt;BR /&gt; ccs_get_config_chain; ccs_error = 0&lt;BR /&gt;ccs_get_config_chain&lt;BR /&gt; serverh = 0&lt;BR /&gt; device_list: (size = 1)&lt;BR /&gt; device[0]:: core_type=mpc603e(31)&lt;BR /&gt; ccs_get_config_chain; ccs_error = 0&lt;BR /&gt;ccs_reset_to_mixed&lt;BR /&gt; chain_pos: (size = 1) { 0 (halt) }&lt;BR /&gt; ccs_reset_to_mixed; ccs_error = 0; duration=405 ms&lt;BR /&gt;ccs_send_message&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; message = 3&lt;BR /&gt; ccs_send_message; ccs_error = 0&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 287&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 80811014&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=3 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; FFF00100&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=1 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2000&lt;BR /&gt; count = 34&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 136)&lt;BR /&gt; 227E227E 00002328 000082A0 00000000&lt;BR /&gt; 00F000F0 24BD4295 00002360 00000000&lt;BR /&gt; FF800100 FF800000 918A4375 00002358&lt;BR /&gt; 00000000 00008270 FFFFFFFF F7FFFFFF&lt;BR /&gt; 24BD4295 3D395017 00000000 B7FFFFFF&lt;BR /&gt; 00000000 FBD67536 00000000 FFFFFFFF&lt;BR /&gt; 00000000 00F000F0 FF800000 FF800000&lt;BR /&gt; FF800000 FFFFFFFF 00000100 00002328&lt;BR /&gt; FFF00100 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=51 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 8&lt;BR /&gt; count = 2&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 8)&lt;BR /&gt; 00000000 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 1&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfff00100]&lt;BR /&gt; data: (size = 256)&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; ccs_read_mem; ccs_error = 0; duration=20 ms&lt;BR /&gt;ccs_read_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfff00200]&lt;BR /&gt; data: (size = 256)&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; ccs_read_mem; ccs_error = 0; duration=20 ms&lt;/P&gt;&lt;P&gt;Executing Initialization File: E:\working\new_git\jg-fmss\04_sw\fmss_app\CFG\fmss_init_CORE.tcl&lt;BR /&gt;thread break: Stopped, 0x0, 0x0, cpuPowerPCBig, Connected (state, tid, pid, cpu, target) &lt;BR /&gt;thread set: Stopped, 0x0, 0x0, cpuPowerPCBig, Connected (state, tid, pid, cpu, target) &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; ccs_stop_core; ccs_error = 0&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt;radix x &lt;BR /&gt; value: (size = 4)&lt;BR /&gt; FFF00100&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfff00100]&lt;BR /&gt;cmdwin::eclipse::config hexprefix 0x &lt;BR /&gt;cmdwin::eclipse::config MemIdentifier v &lt;BR /&gt;cmdwin::eclipse::config MemWidth 32 &lt;BR /&gt;cmdwin::eclipse::config MemAccess 32 &lt;BR /&gt; data: (size = 256)&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; ccs_read_mem; ccs_error = 0; duration=21 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2000&lt;BR /&gt; count = 34&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 136)&lt;BR /&gt; 227E227E 00002328 000082A0 00000000&lt;BR /&gt; 00F000F0 24BD4295 00002360 00000000&lt;BR /&gt; FF800100 FF800000 918A4375 00002358&lt;BR /&gt; 00000000 00008270 FFFFFFFF F7FFFFFF&lt;BR /&gt; 24BD4295 3D395017 00000000 B7FFFFFF&lt;BR /&gt; 00000000 FBD67536 00000000 FFFFFFFF&lt;BR /&gt; 00000000 00F000F0 FF800000 FF800000&lt;BR /&gt; FF800000 FFFFFFFF 00000100 00002328&lt;BR /&gt; FFF00100 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=51 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 8&lt;BR /&gt; count = 2&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 8)&lt;BR /&gt; 00000000 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 1&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;thread break: Stopped, 0x0, 0x0, cpuPowerPCBig, Connected (state, tid, pid, cpu, target) &lt;BR /&gt;cmdwin::eclipse::config MemSwap off &lt;BR /&gt;cmdwin::stop &lt;BR /&gt;cmdwin::wait 0x200 &lt;BR /&gt;cmdwin::reset &lt;BR /&gt;ccs_reset_to_mixed&lt;BR /&gt; chain_pos: (size = 1) { 0 (halt) }&lt;BR /&gt; ccs_reset_to_mixed; ccs_error = 0; duration=405 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; FFF00100&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; FFF00100&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=1 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x04000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 04000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 16bit = 0x600 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:2;address:0xfee00000]&lt;BR /&gt; data: (size = 2)&lt;BR /&gt; 0600&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x80000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 80000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=3 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x84000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 84000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00000000 &lt;BR /&gt; ccs_stop_core; ccs_error = 0&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; FFF00100&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=1 ms&lt;BR /&gt;ccs_read_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfff00100]&lt;BR /&gt; data: (size = 256)&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF&lt;BR /&gt; ccs_read_mem; ccs_error = 0; duration=20 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=1 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2000&lt;BR /&gt; count = 34&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 136)&lt;BR /&gt; 227E227E 00002328 000082A0 00000000&lt;BR /&gt; 00F000F0 24BD4295 00002360 00000000&lt;BR /&gt; FF800100 FF800000 918A4375 00002358&lt;BR /&gt; 00000000 00008270 FFFFFFFF F7FFFFFF&lt;BR /&gt; 24BD4295 3D395017 00000000 B7FFFFFF&lt;BR /&gt; 00000000 FBD67536 00000000 FFFFFFFF&lt;BR /&gt; 00000000 00F000F0 FF800000 FF800000&lt;BR /&gt; FF800000 FFFFFFFF 00000100 00002328&lt;BR /&gt; FFF00100 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=51 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 8&lt;BR /&gt; count = 2&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 8)&lt;BR /&gt; 00000000 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 1&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;thread break: Stopped, 0x0, 0x0, cpuPowerPCBig, Connected (state, tid, pid, cpu, target) &lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x88000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 88000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x8C000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 8C000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=3 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x90000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 90000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0xFF000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; FF000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x94000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 94000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x98000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 98000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x07000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 07000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x9C000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 9C000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xA0000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; A0000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x01000032 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 01000032&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xA8000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; A8000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x981A14FF &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 981A14FF&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xAC000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; AC000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x0C060C00 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 0C060C00&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x78000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 78000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x000000FC &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 000000FC&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xB8000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; B8000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 8bit = 0x0 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:1;address:0xfee00000]&lt;BR /&gt; data: (size = 1)&lt;BR /&gt; 00&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=3 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xF4000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; F4000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0xCC044004 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; CC044004&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xF8000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; F8000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x00004078 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00004078&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xFC000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; FC000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x39323235 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 39323235&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xF0000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; F0000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00000 = 0x0200E875 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfee00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 0200E875&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x72000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 72000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00002 8bit = 0xE0 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:1;address:0xfee00002]&lt;BR /&gt; data: (size = 1)&lt;BR /&gt; E0&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x73000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 73000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00003 8bit = 0xD1 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:1;address:0xfee00003]&lt;BR /&gt; data: (size = 1)&lt;BR /&gt; D1&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=1 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x74000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 74000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=3 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00002 16bit = 0x00FD &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:2;address:0xfee00002]&lt;BR /&gt; data: (size = 2)&lt;BR /&gt; 00FD&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=3 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0x76000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 76000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00002 8bit = 0x40 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:1;address:0xfee00002]&lt;BR /&gt; data: (size = 1)&lt;BR /&gt; 40&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEC00000 = 0xA3000080 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0xfec00000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; A3000080&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0xFEE00003 8bit = 0x32 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:1;address:0xfee00003]&lt;BR /&gt; data: (size = 1)&lt;BR /&gt; 32&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::reg MSR = 0x00001002 &lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2034&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00001002&lt;BR /&gt; ccs_write_register; ccs_error = 0; duration=1 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2034&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00001002&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::mem v:0x700 = 0x48000000 &lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x00000700]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 48000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::reg IABR = 0x702 &lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 1010&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000702&lt;BR /&gt; ccs_write_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 1010&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000702&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;cmdwin::reg SP = 0xF &lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2001&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 0000000F&lt;BR /&gt; ccs_write_register; ccs_error = 0; duration=3 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2001&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 0000000F&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=3 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2000&lt;BR /&gt; count = 34&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 136)&lt;BR /&gt; 227E227E 0000000F 000082A0 00000000&lt;BR /&gt; 00F000F0 24BD4295 00002360 00000000&lt;BR /&gt; FF800100 FF800000 918A4375 00002358&lt;BR /&gt; 00000000 00008270 FFFFFFFF F7FFFFFF&lt;BR /&gt; 24BD4295 3D395017 00000000 B7FFFFFF&lt;BR /&gt; 00000000 FBD67536 00000000 FFFFFFFF&lt;BR /&gt; 00000000 00F000F0 FF800000 FF800000&lt;BR /&gt; FF800000 FFFFFFFF 00000100 00002328&lt;BR /&gt; FFF00100 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=52 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 8&lt;BR /&gt; count = 2&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 8)&lt;BR /&gt; 00000000 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=1 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 1&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=1 ms&lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; ccs_stop_core; ccs_error = 0&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x00000000]&lt;BR /&gt; data: (size = 640)&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 000000FF 000000FF 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; FFFFFFFE 00000000 00000000 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=29 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x000002b0]&lt;BR /&gt; data: (size = 176)&lt;BR /&gt; 00002AF0 00000000 00002B38 00000000&lt;BR /&gt; 38380000 00000000 10080000 00000000&lt;BR /&gt; 10080000 00000000 20080000 00000000&lt;BR /&gt; 28180000 00000000 10080000 00000000&lt;BR /&gt; 00002360 000002A4 000002C0 00002618&lt;BR /&gt; 00000074 000002C8 0000268C 000000C4&lt;BR /&gt; 000002D0 00002750 000000CC 000002D8&lt;BR /&gt; 0000281C 000001C4 000002E0 000029E0&lt;BR /&gt; 00000024 000002E8 00000338 000002F0&lt;BR /&gt; 00002A04 00002360 00000000 00000000&lt;BR /&gt; 00000000 00000000 00000000 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=9 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x00002360]&lt;BR /&gt; data: (size = 3680)&lt;BR /&gt; 9421FFD0 7C0802A6 90010034 39610030&lt;BR /&gt; 4800070D 7C000026 90010010 7C3F0B78&lt;BR /&gt; 3F80FF80 7F9BE378 3BC00000 3BC00000&lt;BR /&gt; 48000018 57DA063E 3F2DFFFF 3B397EF8&lt;BR /&gt; 7F59F1AE 3BDE0001 2E1E0100 4190FFE8&lt;BR /&gt; 3F40FF80 3F2DFFFF 3B397D90 93590004&lt;BR /&gt; 3F2DFFFF 3B397D90 83390000 2E190003&lt;BR /&gt; 419200D0 4090001C 2E190001 41920034&lt;BR /&gt; 409000A4 2E190000 40900018 480001AC&lt;BR /&gt; 2E190005 41920124 409001A0 480000D0&lt;BR /&gt; 3C6DFFFF 38637D90 48000211 480001AC&lt;BR /&gt; 3BA00000 48000048 3800FFFF 3C6DFFFF&lt;BR /&gt; 38637D90 9003000C 3C6DFFFF 38637D90&lt;BR /&gt; 7FA4EB78 48000259 3F2DFFFF 3B397D90&lt;BR /&gt; 9079000C 3F2DFFFF 3B397D90 8339000C&lt;BR /&gt; 2E190000 4092001C 3BBD0001 3F2DFFFF&lt;BR /&gt; 3B397D90 83390008 7E1DC840 4190FFAC&lt;BR /&gt; 3B400000 3F2DFFFF 3B397D90 93590008&lt;BR /&gt; 48000138 3C6DFFFF 38637D90 480002C5&lt;BR /&gt; 3F2DFFFF 3B397D90 9079000C 4800011C&lt;BR /&gt; 3C6DFFFF 38637D90 48000375 3F4DFFFF&lt;BR /&gt; 3B5A7D90 907A000C 3B200000 3F4DFFFF&lt;BR /&gt; 3B5A7D90 933A0008 480000F0 3C6DFFFF&lt;BR /&gt; 38637D90 389F0008 3CADFFFF 38A57E80&lt;BR /&gt; 48000501 3F4DFFFF 3B5A7D90 907A000C&lt;BR /&gt; 833F0008 3F4DFFFF 3B5A7D90 933A0008&lt;BR /&gt; 3F2DFFFF 3B397E80 3F4DFFFF 3B5A7D90&lt;BR /&gt; 933A0010 480000A4 3C6DFFFF 38637D90&lt;BR /&gt; 480002FD 3F2DFFFF 3B397D90 9079000C&lt;BR /&gt; 3F2DFFFF 3B397D90 8339000C 2E190000&lt;BR /&gt; 40920044 3C6DFFFF 38637D90 389F0008&lt;BR /&gt; 3CADFFFF 38A57E80 48000489 833F0008&lt;BR /&gt; 3F4DFFFF 3B5A7D90 933A0008 3F2DFFFF&lt;BR /&gt; 3B397E80 3F4DFFFF 3B5A7D90 933A0010&lt;BR /&gt; 48000038 3B400000 3F2DFFFF 3B397D90&lt;BR /&gt; 93590008 48000024 3B200200 3F4DFFFF&lt;BR /&gt; 3B5A7D90 933A000C 3B200000 3F4DFFFF&lt;BR /&gt; 3B5A7D90 933A0008 3F2000F0 3B3900F0&lt;BR /&gt; 3F4DFFFF 3B5A7D90 835A0004 933A0400&lt;BR /&gt; 7FE00008 48000031 4BFFFDE8 7FEAFB78&lt;BR /&gt; 818A0010 7D8FF120 396A0030 480004E1&lt;BR /&gt; 81410000 800A0004 7D415378 7C0803A6&lt;BR /&gt; 4E800020 00000000 9421FFF0 38210010&lt;BR /&gt; 4E800020 00454E44 9421FFF0 93E1000C&lt;BR /&gt; 93C10008 83E30004 3BC00000 3C8000F0&lt;BR /&gt; 388400F0 909F0000 3C8000AA 388400AA&lt;BR /&gt; 909F1554 3C800055 38840055 909F0AA8&lt;BR /&gt; 3C800090 38840090 909F1554 801F0000&lt;BR /&gt; 900D8014 801F0004 900D8010 3C8000F0&lt;BR /&gt; 388400F0 909F0000 7FC3F378 83E1000C&lt;BR /&gt; 83C10008 38210010 4E800020 9421FFE0&lt;BR /&gt; 93E1001C 93C10018 80A30010 5480103A&lt;BR /&gt; 7FE5002E 3BC00000 3CA00001 38A5F0F0&lt;BR /&gt; B0BF0000 3CA00001 38A59090 B0BF0000&lt;BR /&gt; A01F0004 2C000000 4182000C 38600000&lt;BR /&gt; 48000070 3CA00001 38A5F0F0 B0BF0000&lt;BR /&gt; 380000AA B01F0AAA 38000055 B01F0554&lt;BR /&gt; 38000080 B01F0AAA 380000AA B01F0AAA&lt;BR /&gt; 38000055 B01F0554 38000030 B01F0000&lt;BR /&gt; A01F0000 B0010008 4800000C A01F0000&lt;BR /&gt; B0010008 A0010008 54000630 2C000080&lt;BR /&gt; 4082FFEC 380000F0 B01F0000 7FC3F378&lt;BR /&gt; 83E1001C 83C10018 38210020 4E800020&lt;BR /&gt; 9421FFE0 93E1001C 93C10018 93A10014&lt;BR /&gt; 93810010 38000000 90010008 3BC00000&lt;BR /&gt; 3BA00080 3B800080 83E30004 3C80F0F1&lt;BR /&gt; 3884F0F0 909F0000 3C8000AA 388400AA&lt;BR /&gt; 909F1554 3C800055 38840055 909F0AA8&lt;BR /&gt; 3C800080 38840080 909F1554 3C8000AA&lt;BR /&gt; 388400AA 909F1554 3C800055 38840055&lt;BR /&gt; 909F0AA8 3C800010 38840010 909F1554&lt;BR /&gt; 3C800070 38840070 909F1554 5785043E&lt;BR /&gt; 809F0000 57A0043E 7C800038 7C050040&lt;BR /&gt; 4082FFEC 3C80F0F1 3884F0F0 909F0000&lt;BR /&gt; 7FC3F378 83E1001C 83C10018 83A10014&lt;BR /&gt; 83810010 38210020 4E800020 9421FFC0&lt;BR /&gt; 7C0802A6 90010044 39610040 48000259&lt;BR /&gt; 7C3F0B78 7C7B1B78 38000000 901F001C&lt;BR /&gt; 38000080 B01F000A 38000080 B01F0008&lt;BR /&gt; 83DB0004 57C00024 901F0018 83BB0010&lt;BR /&gt; 801B0008 901F0014 801F0014 5400F87E&lt;BR /&gt; 901F0010 3C600001 3863F0F0 907E0000&lt;BR /&gt; 3C600001 38639090 907E0000 3C600001&lt;BR /&gt; 3863F0F0 907E0000 38000098 807F0018&lt;BR /&gt; B00300AA 380000F0 807F0018 B0030000&lt;BR /&gt; 3C600001 3863F0F0 907E0000 3C600001&lt;BR /&gt; 38639090 907E0000 801F0014 540007FE&lt;BR /&gt; 2C000000 41820030 801F0014 7C1D0214&lt;BR /&gt; 901F000C 380000FF 807F000C 98030000&lt;BR /&gt; 38030001 901F000C 807F0010 38030001&lt;BR /&gt; 901F0010 3C600001 3863F0F0 907E0000&lt;BR /&gt; 38000000 901F0020 4800007C 57DC0024&lt;BR /&gt; 380000AA B01C0AAA 38000055 B01C0554&lt;BR /&gt; 380000A0 B01C0AAA A01D0000 901E0000&lt;BR /&gt; A01F000A 54000630 B01F000A A01D0000&lt;BR /&gt; 54000630 5400043E B01F0008 A01F0008&lt;BR /&gt; 54000630 B01F0008 A09F0008 807E0000&lt;BR /&gt; A01F000A 7C600038 7C040040 4082FFEC&lt;BR /&gt; 3BDE0004 3BBD0002 807F0020 38030001&lt;BR /&gt; 901F0020 807F0020 801F0010 7C030040&lt;BR /&gt; 40800010 801F001C 2C000000 4182FF70&lt;BR /&gt; 3BDEFFFC 380000F0 901E0000 807F001C&lt;BR /&gt; 7FEAFB78 396A0040 4800010D 81410000&lt;BR /&gt; 800A0004 7D415378 7C0803A6 4E800020&lt;BR /&gt; 9421FFF0 93E1000C 93C10008 3BE00000&lt;BR /&gt; 83C30004 83E1000C 83C10008 38210010&lt;BR /&gt; 4E800020 00000000 9421FFF0 7C0802A6&lt;BR /&gt; 90010014 48000020 80030000 3880FFFF&lt;BR /&gt; 900D8018 81830004 80630008 7D8903A6&lt;BR /&gt; 4E800421 806D8018 2C030000 4082FFDC&lt;BR /&gt; 80010014 7C0803A6 38210010 4E800020&lt;BR /&gt; 91CBFFB8 91EBFFBC 920BFFC0 922BFFC4&lt;BR /&gt; 924BFFC8 926BFFCC 928BFFD0 92ABFFD4&lt;BR /&gt; 92CBFFD8 92EBFFDC 930BFFE0 932BFFE4&lt;BR /&gt; 934BFFE8 936BFFEC 938BFFF0 93ABFFF4&lt;BR /&gt; 93CBFFF8 93EBFFFC 4E800020 00000000&lt;BR /&gt; 81CBFFB8 81EBFFBC 820BFFC0 822BFFC4&lt;BR /&gt; 824BFFC8 826BFFCC 828BFFD0 82ABFFD4&lt;BR /&gt; 82CBFFD8 82EBFFDC 830BFFE0 832BFFE4&lt;BR /&gt; 834BFFE8 836BFFEC 838BFFF0 83ABFFF4&lt;BR /&gt; 83CBFFF8 83EBFFFC 4E800020 00000000&lt;BR /&gt; 9421FFF0 7C0802A6 90010014 800D8000&lt;BR /&gt; 2C00FFFE 40820020 38610008 3881000C&lt;BR /&gt; 480003C5 80610008 8081000C 48000055&lt;BR /&gt; 906D8000 80010014 7C0803A6 38210010&lt;BR /&gt; 4E800020 00000000 9421FFF0 7C0802A6&lt;BR /&gt; 90010014 806D8000 2C03FFFE 41820010&lt;BR /&gt; 48000059 3800FFFE 900D8000 80010014&lt;BR /&gt; 7C0803A6 38210010 4E800020 00000000&lt;BR /&gt; 3CAD0000 38A58030 80050008 2C000000&lt;BR /&gt; 4082001C 90650000 38000001 38600000&lt;BR /&gt; 90850004 90050008 4E800020 3860FFFF&lt;BR /&gt; 4E800020 00000000 2C030000 4C820020&lt;BR /&gt; 1C03000C 3C6D0000 38638030 7C630214&lt;BR /&gt; 38000000 90030000 90030004 90030008&lt;BR /&gt; 4E800020 00000000 9421FFF0 7C0802A6&lt;BR /&gt; 90010014 4BFFFE25 818D8020 2C0C0000&lt;BR /&gt; 41820014 7D8903A6 4E800421 38000000&lt;BR /&gt; 900D8020 818D8024 2C0C0000 41820014&lt;BR /&gt; 7D8903A6 4E800421 38000000 900D8024&lt;BR /&gt; 4BFFF9F5 80010014 7C0803A6 38210010&lt;BR /&gt; 4E800020 4E800020 3CA0FFFF 60A5FFF1&lt;BR /&gt; 7CA51838 7C651850 7C841A14 7C0004AC&lt;BR /&gt; 30A50008 3484FFF8 4080FFF4 4C00012C&lt;BR /&gt; 4E800020 3C600001 38638270 7C636850&lt;BR /&gt; 4E800020 7C0802A6 4BFFFFED 28030000&lt;BR /&gt; 41820044 3CA20000 3C820000 38A5AEE0&lt;BR /&gt; 3884AF18 7CC52050 28060000 41820028&lt;BR /&gt; 54C6F0BE 7CC903A6 38A5FFFC 84C50004&lt;BR /&gt; 7CC61A14 80E60000 7CE71A14 90E60000&lt;BR /&gt; 4200FFEC 7C0803A6 4E800020 7C0802A6&lt;BR /&gt; 3DA00001 39AD8270 3C400001 384282A0&lt;BR /&gt; 429F0005 7C8802A6 3C620000 3863AA44&lt;BR /&gt; 7C632050 28030000 4182000C 7DAD1A14&lt;BR /&gt; 7C421A14 3C2D0000 3821A0F0 7C0803A6&lt;BR /&gt; 4E800020 9421FFD0 7C0802A6 90010034&lt;BR /&gt; 39610030 4BFFFD69 4BFFFF3D 9061001C&lt;BR /&gt; 3C620000 3BE3AE78 801F0000 2C000000&lt;BR /&gt; 4082001C 801F0008 2C000000 40820010&lt;BR /&gt; 801F000C 2C000000 418200D0 807F0004&lt;BR /&gt; 801F0000 7C001810 7C000110 7C0000D0&lt;BR /&gt; 90010008 80010008 2C000000 41820028&lt;BR /&gt; 807F0004 8001001C 7C030214 90010010&lt;BR /&gt; 807F0000 8001001C 7C030214 9001000C&lt;BR /&gt; 48000014 801F0000 90010010 801F0004&lt;BR /&gt; 9001000C 807F000C 801F0008 7C001810&lt;BR /&gt; 7C000110 7C0000D0 90010008 80010008&lt;BR /&gt; 2C000000 41820024 807F000C 8001001C&lt;BR /&gt; 7FA30214 807F0008 8001001C 7C030214&lt;BR /&gt; 90010014 48000010 83BF0008 801F000C&lt;BR /&gt; 90010014 80010014 7C1D0050 90010018&lt;BR /&gt; 7FA3EB78 80810010 80A10018 4800014D&lt;BR /&gt; 3BFF0010 4BFFFF14 3C620000 3BC3AEC8&lt;BR /&gt; 801E0000 2C000000 40820010 801E0004&lt;BR /&gt; 2C000000 41820074 807E0004 801E0000&lt;BR /&gt; 7C001810 7C000110 7C0000D0 90010008&lt;BR /&gt; 80010008 2C000000 41820024 807E0004&lt;BR /&gt; 8001001C 7FA30214 807E0000 8001001C&lt;BR /&gt; 7C030214 90010014 48000010 83BE0000&lt;BR /&gt; 801E0004 90010014 80010014 7C1D0050&lt;BR /&gt; 90010018 7FA3EB78 80810018 48000115&lt;BR /&gt; 3BDE0008 4BFFFF7C 4BFFFDBD 39610030&lt;BR /&gt; 4BFFFC1D 80010034 7C0803A6 38210030&lt;BR /&gt; 4E800020 9421FFF0 93E1000C 7C5F1378&lt;BR /&gt; 93E40000 3CA20000 38058098 90030000&lt;BR /&gt; 83E1000C 38210010 4E800020 00000000&lt;BR /&gt; 7C6E1B78 7C8F2378 7CB02B78 4BFFFD29&lt;BR /&gt; 4BFFFDBD 9421FFF8 38000000 90010000&lt;BR /&gt; 3800FFFF 90010004 4BFFFDED 3C620000&lt;BR /&gt; 3863A368 7C6803A6 4E800021 3CC20000&lt;BR /&gt; 38C6A0C0 7CC803A6 7DC37378 7DE47B78&lt;BR /&gt; 7E058378 4E800021 3CC20000 38C6A938&lt;BR /&gt; 7CC803A6 4E800021 9421FFF0 7C0802A6&lt;BR /&gt; 2C050000 90010014 93E1000C 7CBF2B78&lt;BR /&gt; 93C10008 7C7E1B78 4182001C 7C032040&lt;BR /&gt; 41820014 48000045 7FC3F378 7FE4FB78&lt;BR /&gt; 4BFFFC99 80010014 83E1000C 83C10008&lt;BR /&gt; 7C0803A6 38210010 4E800020 00000000&lt;BR /&gt; 2C040000 4D820020 7C852378 38800000&lt;BR /&gt; 48000118 4E800020 7C041840 41800028&lt;BR /&gt; 3884FFFF 38C3FFFF 38A50001 4800000C&lt;BR /&gt; 8C040001 9C060001 34A5FFFF 4082FFF4&lt;BR /&gt; 4E800020 7C842A14 7CC32A14 38A50001&lt;BR /&gt; 48000010 60000000 8C04FFFF 9C06FFFF&lt;BR /&gt; 34A5FFFF 4082FFF4 4E800020 00000000&lt;BR /&gt; 28050020 5487063E 38C3FFFF 41800090&lt;BR /&gt; 7CC030F8 540007BF 41820014 7CA02850&lt;BR /&gt; 3400FFFF 9CE60001 4082FFF8 2C070000&lt;BR /&gt; 4182001C 54E4402E 54E3C00E 54E0801E&lt;BR /&gt; 7CE42378 7C600378 7C870378 54A0D97F&lt;BR /&gt; 3866FFFD 4182002C 90E30004 3400FFFF&lt;BR /&gt; 90E30008 90E3000C 90E30010 90E30014&lt;BR /&gt; 90E30018 90E3001C 94E30020 4082FFDC&lt;BR /&gt; 54A0F77F 41820010 3400FFFF 94E30004&lt;BR /&gt; 4082FFF8 38C30003 54A507BE 2C050000&lt;BR /&gt; 4D820020 60000000 34A5FFFF 9CE60001&lt;BR /&gt; 4082FFF8 4E800020 9421FFF0 7C0802A6&lt;BR /&gt; 90010014 93E1000C 7C7F1B78 4BFFFF35&lt;BR /&gt; 7FE3FB78 83E1000C 80010014 7C0803A6&lt;BR /&gt; 38210010 4E800020 00000270 00000000&lt;BR /&gt; 00000270 00000000 00000280 00000270&lt;BR /&gt; 00000280 00000270 00000360 000002B0&lt;BR /&gt; 00000360 000002B0 000031C0 00002360&lt;BR /&gt; 000031C0 00002360 00000000 00000000&lt;BR /&gt; 00000000 00000000 000002A0 00000280&lt;BR /&gt; 000002B0 000002A0 00000000 00000000&lt;BR /&gt; 000002F0 000002F8 000002FC 00000304&lt;BR /&gt; 00000308 00000310 00000314 0000031C&lt;BR /&gt; 00000320 00000328 0000032C 00000334&lt;BR /&gt; 000002B0 000002B8 00000000 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=157 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x00000000]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x00000010]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 000031C0&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x00000004]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; FF800000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_write_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x0000000c]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_mem; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2013&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_write_register; ccs_error = 0; duration=3 ms&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00002F00&lt;BR /&gt; ccs_write_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00002F00&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_run_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; ccs_run_core; ccs_error = 0&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; index = 2032&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000700&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_mem&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0;size:4;address:0x0000000c]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 15420000&lt;BR /&gt; ccs_read_mem; ccs_error = -2147483639; duration=2 ms&lt;BR /&gt; Error message: target is in unexpected RUNNING mode&lt;BR /&gt;ccs_get_messages&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; message: (size = 0)&lt;BR /&gt; ccs_get_messages; ccs_error = 0&lt;BR /&gt;ccs_close&lt;BR /&gt; serverh = 0&lt;BR /&gt; ccs_close; ccs_error = 0&lt;BR /&gt;ccs_core_run_mode&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; mode = 57996680&lt;BR /&gt; ccs_core_run_mode; ccs_error = 7&lt;BR /&gt; Error message: Invalid handle&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;My ini.tcl file is here:&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;proc init_fmss_cpu {} {&lt;BR /&gt; &lt;BR /&gt; variable SSPR "Standard Special Purpose Registers/" &lt;BR /&gt; &lt;BR /&gt; global IMMRBase&lt;BR /&gt; &lt;BR /&gt; # Set the IMMR so the debugger plugin knows where it is since&lt;BR /&gt; # the IMMR itself is a memory mapped register. This does not&lt;BR /&gt; # actually write anything to the target, it is simply to inform&lt;BR /&gt; # the debugger plugin where the IMMR is&lt;/P&gt;&lt;P&gt;#eppc::setMMRBase $IMMRBase&lt;/P&gt;&lt;P&gt;# relocate internal memory space&lt;BR /&gt; # IMMR&lt;BR /&gt;#mem [IMMR 0x101A8] = 0x04700000 &lt;BR /&gt; &lt;BR /&gt;#set IMMRBase 0x04700000&lt;BR /&gt;#eppc::setMMRBase $IMMRBase&lt;/P&gt;&lt;P&gt;# Main System Clock Configuration Registers &lt;BR /&gt; # Machine Mode Register&lt;BR /&gt;#reg ${SSPR}MSR = 0x1002&lt;/P&gt;&lt;P&gt;# PDTEM&lt;BR /&gt;#mem [IMMR 0x10054] 8bit = 0x00 &lt;BR /&gt; # RMR &lt;BR /&gt;#mem [IMMR 0x10C94] 16bit = 0x0001&lt;/P&gt;&lt;P&gt;# Setup the chip selects&lt;/P&gt;&lt;P&gt;#mem v:0x00000000 8bit = 0xFF&lt;BR /&gt; #CBR refresh.&lt;BR /&gt; &lt;BR /&gt; mem v:0xFEC00000 = 0x04000080&lt;BR /&gt; mem v:0xFEE00000 16bit = 0x600; # bus master and responds to pci memory&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0x80000080; # starting_address_1&lt;BR /&gt; mem v:0xFEE00000 = 0x00000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x84000080; # starting_address_2&lt;BR /&gt; mem v:0xFEE00000 = 0x00000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x88000080; # extended_starting_address_1&lt;BR /&gt; mem v:0xFEE00000 = 0x00000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x8C000080; # extended_starting_address_2&lt;BR /&gt; mem v:0xFEE00000 = 0x00000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x90000080; # mem_ending_address_1&lt;BR /&gt; mem v:0xFEE00000 = 0xFF000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x94000080; # mem_ending_address_2&lt;BR /&gt; mem v:0xFEE00000 = 0x00000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x98000080; # extended_mem_ending_address_1&lt;BR /&gt; mem v:0xFEE00000 = 0x07000000;&lt;BR /&gt; mem v:0xFEC00000 = 0x9C000080; # extended_mem_ending_address_2&lt;BR /&gt; mem v:0xFEE00000 = 0x00000000;&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0xA0000080; # bank 0 enable&lt;BR /&gt; mem v:0xFEE00000 = 0x01000032;&lt;BR /&gt; &lt;BR /&gt; mem v:0xFEC00000 = 0xA8000080; # PICR_1&lt;BR /&gt; #mem v:0xFEE00000 = 0x901A1400; # map B, flash write, processor parked on the data bus&lt;BR /&gt; mem v:0xFEE00000 = 0x981A14FF; # map B, flash write, processor parked on the data bus&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0xAC000080; # PICR_2&lt;BR /&gt; mem v:0xFEE00000 = 0x0C060C00; # ROM/Flash WR lockout disable&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0x78000080; # EUMBBAR&lt;BR /&gt; mem v:0xFEE00000 = 0x000000FC; # 0xFC000000&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0xB8000080; # ECC error&lt;BR /&gt; mem v:0xFEE00000 8bit = 0x0;&lt;BR /&gt; &lt;BR /&gt;# ----- Enable memory, 8-bit data path for ROM back 0, enable refresh&lt;BR /&gt;# ----- during sleep, RAM type = SDRAM, 11 or 12 row bits&lt;BR /&gt; mem v:0xFEC00000 = 0xF4000080; # MCCR_2&lt;BR /&gt; mem v:0xFEE00000 = 0xCC044004;&lt;BR /&gt; mem v:0xFEC00000 = 0xF8000080; # MCCR_3&lt;BR /&gt; mem v:0xFEE00000 = 0x00004078;&lt;BR /&gt; mem v:0xFEC00000 = 0xFC000080; # MCCR_4&lt;BR /&gt; mem v:0xFEE00000 = 0x39323235;&lt;BR /&gt; mem v:0xFEC00000 = 0xF0000080; # MCCR_1&lt;BR /&gt; mem v:0xFEE00000 = 0x0200E875;&lt;BR /&gt; &lt;BR /&gt; mem v:0xFEC00000 = 0x72000080; # PMCR_2&lt;BR /&gt; mem v:0xFEE00002 8bit = 0xE0; # refresh sdram during sleep&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0x73000080; # ODCR&lt;BR /&gt; mem v:0xFEE00003 8bit = 0xD1;&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0x74000080; # CDCR&lt;BR /&gt; mem v:0xFEE00002 16bit = 0x00FD;&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0x76000080; # MDCR&lt;BR /&gt; mem v:0xFEE00002 8bit = 0x40;&lt;/P&gt;&lt;P&gt;mem v:0xFEC00000 = 0xA3000080; # PGMAX&lt;BR /&gt; mem v:0xFEE00003 8bit = 0x32;&lt;/P&gt;&lt;P&gt;reg MSR = 0x00001002; # machine check exceptions enable, Vector=0x000n_nnnn&lt;/P&gt;&lt;P&gt;#;valid opcode at program exception&lt;BR /&gt; mem v:0x700 = 0x48000000;&lt;/P&gt;&lt;P&gt;# breakpoint at 0x700 - necessary for flash programmer&lt;BR /&gt; reg IABR = 0x702; # 0x700 is addr, 2 is enable&lt;/P&gt;&lt;P&gt;reg SP = 0xF; # prevent stack walk&lt;BR /&gt; &lt;BR /&gt; # perform 8 accesses&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;BR /&gt;# mem v:0x00000000 8bit = 0xFF&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P&gt;proc envsetup {} {&lt;BR /&gt; # Environment Setup&lt;BR /&gt; radix x &lt;BR /&gt; config hexprefix 0x&lt;BR /&gt; config MemIdentifier v&lt;BR /&gt; config MemWidth 32 &lt;BR /&gt; config MemAccess 32 &lt;BR /&gt; config MemSwap off&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;#-------------------------------------------------------------------------------&lt;BR /&gt;# Main &lt;BR /&gt;#-------------------------------------------------------------------------------&lt;/P&gt;&lt;P&gt;envsetup&lt;BR /&gt; &lt;BR /&gt; stop&lt;BR /&gt; wait 0x200&lt;BR /&gt; reset&lt;/P&gt;&lt;P&gt;init_fmss_cpu&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 23 Mar 2020 05:57:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Issue-for-MPC8245-flash-program/m-p/1000528#M3111</guid>
      <dc:creator>gang_liu</dc:creator>
      <dc:date>2020-03-23T05:57:36Z</dc:date>
    </item>
    <item>
      <title>Re: Issue for MPC8245 flash program</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Issue-for-MPC8245-flash-program/m-p/1000529#M3112</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello&amp;nbsp;&lt;A _jive_internal="true" data-content-finding="Community" data-userid="357031" data-username="gang.liu@honfei.cn" href="https://community.nxp.com/people/gang.liu@honfei.cn" style="color: #3d9ce7; background-color: #ffffff; border: 0px; font-weight: 600; text-decoration: none; font-size: 11.9994px;"&gt;gang liu&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In your CCS log, there is problem to read memory &lt;SPAN&gt;0x0000000c&lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;,&amp;nbsp;probably&amp;nbsp;&lt;SPAN&gt;SDRAM configuration section in CW initialization file is not totally suitable for your custom board.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;Would you please do memory test from Tools-&amp;gt;Hardware Diagnostics in CodeWarrior IDE?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;After filled Configuration panel for your custom board, please do Memory Read/Write test at&amp;nbsp;&lt;SPAN style="color: #3d3d3d;"&gt;0x0000000c.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&lt;SPAN&gt;Yiping&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 24 Mar 2020 05:52:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Issue-for-MPC8245-flash-program/m-p/1000529#M3112</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2020-03-24T05:52:00Z</dc:date>
    </item>
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