PowerQUICC ProcessorsのトピックMPC8358E interface to DDR chipset

MPC8358E interface to DDR chipset

venkat1 — Fri, 15 Nov 2019 05:51:45 GMT

Hello All,

The following clarifications are required in interfacing MPC8358, Power QUICC II Pro Processor to a 256Mbit DDR memory device through the Primary DDR controller block of MPC8358

Does End-ianness matters in connecting the DAT bus MDQ[0:31] to the DDR Device…

Ref: MPC8360E reference Manual (MPC5360ERM Rev 3 05/2010)

Page: Chapter 9, Page 43…9-43…Fig 9.34

In the above Fig, its shown that, MDQ0 is conn to DQ[7] of the RAM & MDQ7 is conn to DQ[0] & so on……

Whether this type of swapping is required as we do in the Local Bus section

Is it mandatory to use error correction (ECC), as there is an option to enable or disable ERROR correction
Is there a ref sch where MPC8358 DDR controller is directly interfaced to a DDR chipset & not to a SODIMM module Regards,
Venkat 8495952871or 98862 01027

Re: MPC8358E interface to DDR chipset

r8070z — Mon, 18 Nov 2019 15:25:50 GMT

1 DDR byte lanes can be swapped and in each byte lane bits can be swapped too.

2 It is not mandatory to use error correction (ECC). It can be enabled or disabled by DDR_SDRAM_CFG[ECC_EN].

3 There was MPC8360 - SOM where MPC8360 DDR controller was directly interfaced to four 16-bit DDR chips.

Re: MPC8358E interface to DDR chipset

venkat1 — Tue, 19 Nov 2019 07:09:01 GMT

Thank you sir..

can you plz send mpc8360 SOM schematic, where 16-bit DDR chip is directly interfaced with mpc8360.

regards,

venkat.

Re: MPC8358E interface to DDR chipset

r8070z — Wed, 20 Nov 2019 04:41:14 GMT

I afraid it cannot be shared publicly. Please create special request. See

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