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    <title>PowerQUICC Processors中的主题 about mpc8358 proccessor interface with DDR SDRAM.</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/about-mpc8358-proccessor-interface-with-DDR-SDRAM/m-p/978032#M3052</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; We are using MPC8358, PowerQUICC II Pro family of Processor in our design.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; Require Tech material or ref SCH in interfacing the MPC8358 Processor with DDR SDRAM.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;REgards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Venkat&lt;/P&gt;&lt;P&gt;8495952871&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Balaji&lt;/P&gt;&lt;P&gt;98862 01027&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 12 Nov 2019 05:16:19 GMT</pubDate>
    <dc:creator>venkat1</dc:creator>
    <dc:date>2019-11-12T05:16:19Z</dc:date>
    <item>
      <title>about mpc8358 proccessor interface with DDR SDRAM.</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/about-mpc8358-proccessor-interface-with-DDR-SDRAM/m-p/978032#M3052</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; We are using MPC8358, PowerQUICC II Pro family of Processor in our design.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; Require Tech material or ref SCH in interfacing the MPC8358 Processor with DDR SDRAM.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;REgards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Venkat&lt;/P&gt;&lt;P&gt;8495952871&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Balaji&lt;/P&gt;&lt;P&gt;98862 01027&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 12 Nov 2019 05:16:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/about-mpc8358-proccessor-interface-with-DDR-SDRAM/m-p/978032#M3052</guid>
      <dc:creator>venkat1</dc:creator>
      <dc:date>2019-11-12T05:16:19Z</dc:date>
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      <title>Re: about mpc8358 proccessor interface with DDR SDRAM.</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/about-mpc8358-proccessor-interface-with-DDR-SDRAM/m-p/978033#M3053</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The only available schematic example is the schematics of the 'MPC8360EA Modular Development System', MPC8360EAMDS:&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/downloads/en/schematics/MPC8360EAMDSSCH.pdf" title="https://www.nxp.com/downloads/en/schematics/MPC8360EAMDSSCH.pdf"&gt;https://www.nxp.com/downloads/en/schematics/MPC8360EAMDSSCH.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This board uses two SODIMMs interfaced to the MPC8360 to get functionality of two memory controllers. In your case (MPC8358, single memory controller) you need to take a look at U33 SODIMM only.&lt;/P&gt;&lt;P&gt;Note also that TBGA package is used in the schematics, if you are going to use PBGA package, pin numbering needs to be changed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Bulat&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 13 Nov 2019 07:07:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/about-mpc8358-proccessor-interface-with-DDR-SDRAM/m-p/978033#M3053</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2019-11-13T07:07:04Z</dc:date>
    </item>
    <item>
      <title>Re: about mpc8358 proccessor interface with DDR SDRAM.</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/about-mpc8358-proccessor-interface-with-DDR-SDRAM/m-p/978034#M3054</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you. mr.Bulat Karymov.&lt;/P&gt;&lt;P&gt;we are using two&amp;nbsp; ddr sdram&amp;nbsp; size of&amp;nbsp; 256Mb (16M16 config.) for achieving 32-bit data bus.&amp;nbsp; please suggest us how this&amp;nbsp; cs#&amp;nbsp; and logical banks&amp;nbsp; config.? so that we communicate 32-bit data with sdram and mpc8358 ..&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thank you regards,&lt;/P&gt;&lt;P&gt;venkat.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 13 Nov 2019 10:31:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/about-mpc8358-proccessor-interface-with-DDR-SDRAM/m-p/978034#M3054</guid>
      <dc:creator>venkat1</dc:creator>
      <dc:date>2019-11-13T10:31:37Z</dc:date>
    </item>
    <item>
      <title>Re: about mpc8358 proccessor interface with DDR SDRAM.</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/about-mpc8358-proccessor-interface-with-DDR-SDRAM/m-p/978035#M3055</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;You need to use a single CS (CS0) and four byte lanes (MDQ0..MDQ31) for your configuration.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Bulat&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 Nov 2019 11:38:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/about-mpc8358-proccessor-interface-with-DDR-SDRAM/m-p/978035#M3055</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2019-11-14T11:38:43Z</dc:date>
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