topic e500 core revision in PowerQUICC Processors

e500 core revision

benjaminchauvel — Fri, 30 Aug 2019 14:02:16 GMT

Hello,

i was reading an interesting answer about Application Note AN3532 and CPU30 Erratum : https://community.nxp.com/message/435201?commentID=435201#comment-435201

I'm looking for an official document describing e500 core revision for P2020 so i can do only step 2. 3. 4. and 5 for instruction cache parity error handling ( if i'm correct, I don't want to do a full cache invalidation ) .

An official answer on your forum may not be enough for QA department. Do you know where can i found that information ?

Thanks.

Benjamin

Re: e500 core revision

ufedor — Fri, 30 Aug 2019 17:11:43 GMT

P2020 silicon Rev 1.0 has e500 core Rev 4.0

P2020 silicon Rev 2.0 has e500 core Rev 5.0

P2020 silicon Rev 2.1 has e500 core Rev 5.1

From the P2020 QorIQ Integrated Processor Hardware Specifications, 4.2.1 Part Marking

P2020xtencdr

r - Silicon (die) revision:

A = Rev 1.0
B = Rev 2.0
C = Rev 2.1

Re: e500 core revision

benjaminchauvel — Mon, 02 Sep 2019 08:02:11 GMT

thank you