PowerQUICC Processors中的主题 MPC870 RESET https://community.nxp.com/t5/PowerQUICC-Processors/MPC870-RESET/m-p/826200#M2549 <HTML><HEAD></HEAD><BODY><P>Hello,<BR />My question are related to the MPC870.</P><OL><LI>Is s/w watchdog reset reflected on the HRESET* pin? My observations show it is not but the reset process is carried out. I would like your confirmation.</LI><LI>The above question follows behavior depicted on the attached picture. I see HRESET* asserted (for unknown reason at this point). The boot process starts but soon the HRESET* asserted again. this scenario repeats itself several times and eventually the HRESET* stays asserted until I (manually) power it up. As said, I do not know what cause the reset at the middle of of work (under investigation, likely h/w issue). Has somebody encountered this scenario or has explanation for this.</LI><LI>In order to generate check-stop case I did the following:<BR /> Setting PLPRCR[CSR] bit.<BR /> Clearing MSR[ME] bit.<BR /> Clearing MSR[DR] bit (to avoid MMU exception).<BR /> Access none-existing address.</LI></OL><P>I have experienced check-stop but the RSR[SWRS] was set rather than RSR[CSRS], meaning the s/w watchdog took the lead. If I repeat the above steps after disabling the the s/w watchdog the device was halted but no reset followed. Any idea?</P><P></P><P>Thank You</P><P>David</P></BODY></HTML> Fri, 14 Sep 2018 16:14:53 GMT MPC8313ERDB_h 2018-09-14T16:14:53Z MPC870 RESET https://community.nxp.com/t5/PowerQUICC-Processors/MPC870-RESET/m-p/826200#M2549 <HTML><HEAD></HEAD><BODY><P>Hello,<BR />My question are related to the MPC870.</P><OL><LI>Is s/w watchdog reset reflected on the HRESET* pin? My observations show it is not but the reset process is carried out. I would like your confirmation.</LI><LI>The above question follows behavior depicted on the attached picture. I see HRESET* asserted (for unknown reason at this point). The boot process starts but soon the HRESET* asserted again. this scenario repeats itself several times and eventually the HRESET* stays asserted until I (manually) power it up. As said, I do not know what cause the reset at the middle of of work (under investigation, likely h/w issue). Has somebody encountered this scenario or has explanation for this.</LI><LI>In order to generate check-stop case I did the following:<BR /> Setting PLPRCR[CSR] bit.<BR /> Clearing MSR[ME] bit.<BR /> Clearing MSR[DR] bit (to avoid MMU exception).<BR /> Access none-existing address.</LI></OL><P>I have experienced check-stop but the RSR[SWRS] was set rather than RSR[CSRS], meaning the s/w watchdog took the lead. If I repeat the above steps after disabling the the s/w watchdog the device was halted but no reset followed. Any idea?</P><P></P><P>Thank You</P><P>David</P></BODY></HTML> Fri, 14 Sep 2018 16:14:53 GMT https://community.nxp.com/t5/PowerQUICC-Processors/MPC870-RESET/m-p/826200#M2549 MPC8313ERDB_h 2018-09-14T16:14:53Z Re: MPC870 RESET https://community.nxp.com/t5/PowerQUICC-Processors/MPC870-RESET/m-p/826201#M2550 <HTML><HEAD></HEAD><BODY><P><SPAN style="font-size: 10.0pt; color: black;">Check the </SPAN><SPAN style="font-size: 10.0pt;">Debug Enable Register (DER) value for reset generation from checkstop.</SPAN></P><P><BR />Have a great day,<BR />Pavel Chubakov</P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Tue, 02 Oct 2018 05:43:26 GMT https://community.nxp.com/t5/PowerQUICC-Processors/MPC870-RESET/m-p/826201#M2550 Pavel 2018-10-02T05:43:26Z