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    <title>topic T4240_PCIE in PowerQUICC Processors</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/T4240-PCIE/m-p/734642#M2283</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I designed the circuit on the T4240 chip through the PCIE connected to the bridge（PCIE-SATA ）, but at low temperatures through the PCIE can not recognize the bridge.&lt;/P&gt;&lt;P&gt;What is the maximum length of chip（T4240) support in PCIE2.0?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 31 Oct 2017 07:10:21 GMT</pubDate>
    <dc:creator>jeffcao</dc:creator>
    <dc:date>2017-10-31T07:10:21Z</dc:date>
    <item>
      <title>T4240_PCIE</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/T4240-PCIE/m-p/734642#M2283</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I designed the circuit on the T4240 chip through the PCIE connected to the bridge（PCIE-SATA ）, but at low temperatures through the PCIE can not recognize the bridge.&lt;/P&gt;&lt;P&gt;What is the maximum length of chip（T4240) support in PCIE2.0?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 31 Oct 2017 07:10:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/T4240-PCIE/m-p/734642#M2283</guid>
      <dc:creator>jeffcao</dc:creator>
      <dc:date>2017-10-31T07:10:21Z</dc:date>
    </item>
    <item>
      <title>Re: T4240_PCIE</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/T4240-PCIE/m-p/734643#M2284</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="font-size: 10.0pt;"&gt;Look at attached files. These files contain recommendations for PCI layout and information about maximum length.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Pavel Chubakov&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Nov 2017 02:23:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/T4240-PCIE/m-p/734643#M2284</guid>
      <dc:creator>Pavel</dc:creator>
      <dc:date>2017-11-02T02:23:52Z</dc:date>
    </item>
    <item>
      <title>Re: T4240_PCIE</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/T4240-PCIE/m-p/734644#M2285</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi pavel&lt;/P&gt;&lt;P&gt;In attached files,I dont find about&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt; PCI layout and design guide&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Thankyou&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Nov 2017 02:41:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/T4240-PCIE/m-p/734644#M2285</guid>
      <dc:creator>jeffcao</dc:creator>
      <dc:date>2017-11-03T02:41:38Z</dc:date>
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