PowerQUICC ProcessorsのトピックRe: HDLC_RX_CR and HDLC_RX_NO error and data length is 1

HDLC_RX_CR and HDLC_RX_NO error and data length is 1

mdmuazzam — Wed, 28 Feb 2018 10:49:43 GMT

Hi,

I have written hdlc driver for freescale mpc8309twr board,and i am getting CRC error on receive and non-octet aligned as well as with the help of bd_status , i am getting length of packet equal to 1 , So where i am doing any mistake.

And at the time of sending packet i am instructing hdlc controller to add CRC ,so even i am getting reply for a packet but lenght with one.

My setup is like that : Router1(mpc8309) ----> modem(v.35 to dsl converter)-------->modem(dsl to v.35 converter)---->Router2(mpc8309)

Your answer is appreciated.

Thanks

Muazzam(india)

Re: HDLC_RX_CR and HDLC_RX_NO error and data length is 1

alexander_yakov — Tue, 06 Mar 2018 06:53:57 GMT

Typical reason for "Non-octet aligned frame" error is excessive noise on clock input, this is used to sample incoming data. Please check if input clock waveform is correct and clock source output impedance is matched with trace impedance.

Have a great day,
Alexander
TIC

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Re: HDLC_RX_CR and HDLC_RX_NO error and data length is 1

mdmuazzam — Tue, 06 Mar 2018 11:23:50 GMT

Thanks Alexander,

But when my device is connected to slave mode modem (which gives me clock tx and rx both) then its working fine .

what happens when we connect with Master mode modem.

Basically in CRO i observed ,that i am getting distorted RX input clock in Master mode modem but very clear input clock in slave mode.

And also tested modems in tester and found modem correct.

So what kind of circuit may distort the signal?.

Thanks

Muazzam(india)

Re: HDLC_RX_CR and HDLC_RX_NO error and data length is 1

mdmuazzam — Tue, 06 Mar 2018 12:54:56 GMT

Hi,

Can i use Received frames threshold(RFTHR) register to minimize the effect of Non-aligned octed issue due to excessive noise in input clock.

Re: HDLC_RX_CR and HDLC_RX_NO error and data length is 1

alexander_yakov — Tue, 06 Mar 2018 16:02:16 GMT

Please submit scope pictures of "distorted RX input clock in Master mode" and "clear input clock in slave mode".

Also please describe your hardware connections to between MPC8309 and modem.

Re: HDLC_RX_CR and HDLC_RX_NO error and data length is 1

alexander_yakov — Tue, 06 Mar 2018 17:17:18 GMT

No, I do not think this will be helpful

Re: HDLC_RX_CR and HDLC_RX_NO error and data length is 1

mdmuazzam — Mon, 12 Mar 2018 07:32:05 GMT

Hi alex,

Can you tell me how can i reduce noise according to you which is input signal?.

Re: HDLC_RX_CR and HDLC_RX_NO error and data length is 1

mdmuazzam — Tue, 13 Mar 2018 10:20:20 GMT

Hi alex,

I have changed clock number ,i.e RXLCK =14 for UCC5 in mpc8309 and TXCLK =13,so now i just reversed and it's working .

So my doubt is why d i need to interchange the clock numbers in UCC.Is it one kind of bug in MPC8309 Processor ?.

Thanks

Muazzam(india)

Re: HDLC_RX_CR and HDLC_RX_NO error and data length is 1

alexander_yakov — Thu, 15 Mar 2018 02:45:06 GMT

If my understanding is correct, this means your external connection is done in this way. I mean, TX clock is connected to RX clock input and viceversa.

Re: HDLC_RX_CR and HDLC_RX_NO error and data length is 1

mdmuazzam — Thu, 15 Mar 2018 09:14:28 GMT

No alex , all connections are correct ,recently i seen in revision 1 of mpc8309RM manual they have mentioned that clock numbers have to interchanged.

Alex if you can tell ,diiferent then HDLC, Why do we need to change the base address of IMMRBAR from FF40_0000 to e000_0000 in init.cfg file which is given by freescale?

Thanks

Muazzam(india)

Re: HDLC_RX_CR and HDLC_RX_NO error and data length is 1

alexander_yakov — Fri, 16 Mar 2018 16:07:21 GMT

Yes, you are right. I usually assume customers use most recent revisions of of our documents.

Internal space can be moved from its default position to any other place, if necessary. This is done by writing to IMMRBAR. Usually, IMMR is moved because upper part of memory is used for NOR flash, however this depends on flash size, so - up to designer.