<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Timeout error while waiting for FLG bit in CPCR register to be cleared in PowerQUICC Processors</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/Timeout-error-while-waiting-for-FLG-bit-in-CPCR-register-to-be/m-p/689184#M2149</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The issue is related to the timeout error while waiting for the Communications Processor to clear the FLG bit in CPCR register (CP Command Register).&lt;/P&gt;&lt;P&gt;The operation is when the FLG bit is set, we cannot give another command. Only when the CP clears the FLG bit set by Core, we can give other commands.&lt;/P&gt;&lt;P&gt;The SCCx (where x is from 1 to 4) for UARTs is configured as per section 21.21 in the MPC8280 Reference Manual. We are waiting on the CPCR FLG bit to be cleared for 6 SECONDS. But we still &lt;BR /&gt;see the timeout and the FLG bit is not cleared by Communications Processor.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Reference: MPC8280RM which can be found in &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.nxp.com%2Fdocs%2Fen%2Freference-manual%2FMPC8280RM.pdf" rel="nofollow" target="_blank"&gt;http://www.nxp.com/docs/en/reference-manual/MPC8280RM.pdf&lt;/A&gt;&lt;SPAN&gt;.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 31 Jul 2017 11:29:15 GMT</pubDate>
    <dc:creator>rvijay435</dc:creator>
    <dc:date>2017-07-31T11:29:15Z</dc:date>
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      <title>Timeout error while waiting for FLG bit in CPCR register to be cleared</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Timeout-error-while-waiting-for-FLG-bit-in-CPCR-register-to-be/m-p/689184#M2149</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The issue is related to the timeout error while waiting for the Communications Processor to clear the FLG bit in CPCR register (CP Command Register).&lt;/P&gt;&lt;P&gt;The operation is when the FLG bit is set, we cannot give another command. Only when the CP clears the FLG bit set by Core, we can give other commands.&lt;/P&gt;&lt;P&gt;The SCCx (where x is from 1 to 4) for UARTs is configured as per section 21.21 in the MPC8280 Reference Manual. We are waiting on the CPCR FLG bit to be cleared for 6 SECONDS. But we still &lt;BR /&gt;see the timeout and the FLG bit is not cleared by Communications Processor.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Reference: MPC8280RM which can be found in &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.nxp.com%2Fdocs%2Fen%2Freference-manual%2FMPC8280RM.pdf" rel="nofollow" target="_blank"&gt;http://www.nxp.com/docs/en/reference-manual/MPC8280RM.pdf&lt;/A&gt;&lt;SPAN&gt;.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 31 Jul 2017 11:29:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Timeout-error-while-waiting-for-FLG-bit-in-CPCR-register-to-be/m-p/689184#M2149</guid>
      <dc:creator>rvijay435</dc:creator>
      <dc:date>2017-07-31T11:29:15Z</dc:date>
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      <title>Re: Timeout error while waiting for FLG bit in CPCR register to be cleared</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Timeout-error-while-waiting-for-FLG-bit-in-CPCR-register-to-be/m-p/689185#M2150</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Before sending any command to CPCR register please perform the following.&lt;/P&gt;&lt;P&gt;1. Clear entire DPRAM by filling it by zeros&lt;/P&gt;&lt;P&gt;2. Issue "reset" command by setting CPCR[RST] along with CPCR[FLG] flag.&lt;/P&gt;&lt;P&gt;3. Wait for FLG bit cleared.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;After this procedure you can begin initialization of CPM peripherals and issue commands to CPCR.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Alexander&lt;BR /&gt;TIC&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Aug 2017 04:39:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Timeout-error-while-waiting-for-FLG-bit-in-CPCR-register-to-be/m-p/689185#M2150</guid>
      <dc:creator>alexander_yakov</dc:creator>
      <dc:date>2017-08-02T04:39:56Z</dc:date>
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      <title>Re: Timeout error while waiting for FLG bit in CPCR register to be cleared</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Timeout-error-while-waiting-for-FLG-bit-in-CPCR-register-to-be/m-p/689186#M2151</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Alexander,&lt;/P&gt;&lt;P&gt;Thanks for the response.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;And one more doubt, is there any specific time I have to wait fro FLG bit to be cleared??? Like few milli-seconds?&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Aug 2017 07:16:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Timeout-error-while-waiting-for-FLG-bit-in-CPCR-register-to-be/m-p/689186#M2151</guid>
      <dc:creator>rvijay435</dc:creator>
      <dc:date>2017-08-02T07:16:28Z</dc:date>
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      <title>Re: Timeout error while waiting for FLG bit in CPCR register to be cleared</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Timeout-error-while-waiting-for-FLG-bit-in-CPCR-register-to-be/m-p/689187#M2152</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Our documentation does not specify this time, but yes, it should be significantly less than mentioned 6 seconds.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 03 Aug 2017 03:57:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Timeout-error-while-waiting-for-FLG-bit-in-CPCR-register-to-be/m-p/689187#M2152</guid>
      <dc:creator>alexander_yakov</dc:creator>
      <dc:date>2017-08-03T03:57:07Z</dc:date>
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      <title>Re: Timeout error while waiting for FLG bit in CPCR register to be cleared</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/Timeout-error-while-waiting-for-FLG-bit-in-CPCR-register-to-be/m-p/689188#M2153</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Sure.&lt;/P&gt;&lt;P&gt;Thanks Alexander.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 03 Aug 2017 05:35:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/Timeout-error-while-waiting-for-FLG-bit-in-CPCR-register-to-be/m-p/689188#M2153</guid>
      <dc:creator>rvijay435</dc:creator>
      <dc:date>2017-08-03T05:35:18Z</dc:date>
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  </channel>
</rss>

