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    <title>topic MPC8272 Write-through cache OK, write-back not in PowerQUICC Processors</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8272-Write-through-cache-OK-write-back-not/m-p/127962#M2</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Question from newsgroup:&lt;BR /&gt;&lt;BR /&gt;Write-through cache OK, write-back not&lt;BR /&gt;----------------------------------------------&lt;BR /&gt;I have a strange problem. I have a program that runs fine with write- through&lt;BR /&gt;cache, but not with write-back. It is not a multi-threaded program, the&lt;BR /&gt;application is single-threaded. It is running after a boot from u-boot on an&lt;BR /&gt;8272. Could I have something set wrong in the SDRAM controller that would&lt;BR /&gt;cause this? - Sat, Mar 24 2007 8:39 pm&lt;BR /&gt;&lt;BR /&gt;A&amp;gt; Could this be a synchronization issue? Are you jumping from flash to SDRAM? When you initially copy your image over to SDRAM you want to make sure the SDRAM is marked as non-executable and cache-inhibited, at least until you have the image over there. Then make the changes in the MMU and do the jump.&lt;BR /&gt;&lt;BR /&gt;What are your BAT or TLB entry attributes for the area you are trying to execute from? How do you do the jump? Any sync statements in there before you jump? Is this a branch absolute?&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 27 Mar 2007 00:31:25 GMT</pubDate>
    <dc:creator>genuap</dc:creator>
    <dc:date>2007-03-27T00:31:25Z</dc:date>
    <item>
      <title>MPC8272 Write-through cache OK, write-back not</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8272-Write-through-cache-OK-write-back-not/m-p/127962#M2</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Question from newsgroup:&lt;BR /&gt;&lt;BR /&gt;Write-through cache OK, write-back not&lt;BR /&gt;----------------------------------------------&lt;BR /&gt;I have a strange problem. I have a program that runs fine with write- through&lt;BR /&gt;cache, but not with write-back. It is not a multi-threaded program, the&lt;BR /&gt;application is single-threaded. It is running after a boot from u-boot on an&lt;BR /&gt;8272. Could I have something set wrong in the SDRAM controller that would&lt;BR /&gt;cause this? - Sat, Mar 24 2007 8:39 pm&lt;BR /&gt;&lt;BR /&gt;A&amp;gt; Could this be a synchronization issue? Are you jumping from flash to SDRAM? When you initially copy your image over to SDRAM you want to make sure the SDRAM is marked as non-executable and cache-inhibited, at least until you have the image over there. Then make the changes in the MMU and do the jump.&lt;BR /&gt;&lt;BR /&gt;What are your BAT or TLB entry attributes for the area you are trying to execute from? How do you do the jump? Any sync statements in there before you jump? Is this a branch absolute?&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Mar 2007 00:31:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8272-Write-through-cache-OK-write-back-not/m-p/127962#M2</guid>
      <dc:creator>genuap</dc:creator>
      <dc:date>2007-03-27T00:31:25Z</dc:date>
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