PowerQUICC ProcessorsのトピックRe: Linux Driver for QE UMCC

Linux Driver for QE UMCC

aleksandargeras — Thu, 09 Mar 2017 11:57:49 GMT

Hello,

We are currently working on a product based on T1040, and we are planning to use QE UMCC for implementing TDM link.

We are estimating needed effort for implementing this in Linux Kernel, so far we have seen that there is no available UMCC driver.

So our question is:

Is there currently publicly available Linux Kernel driver that uses UMCC functionality, or is there a plan in near future such a driver to be available?

Regards,

Aleksandar

Re: Linux Driver for QE UMCC

Pavel — Wed, 15 Mar 2017 12:29:32 GMT

Use SDK 2.0 for the T1040 board. Look at kernel menu configuration from this SDK.

Device Drivers --->

[*] Wan interfaces support --->

<*> Generic HDLC layer

<*> Freescale QUICC Engine HDLC support

Have a great day,
Pavel Chubakov

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Re: Linux Driver for QE UMCC

aleksandargeras — Thu, 16 Mar 2017 23:50:22 GMT

Hi Pavel,

Thanks for your answer, we are aware of fsl_ucc_hdlc driver, the question is not regarding ucc hdlc driver.

We are planning to use umcc (replacement for mcc in T1040 QuiccEngine) for implementing 8 independent 2Mbps

TDM lines using UMCC and one of the available TDMs (TDMA or TDMB).

Current kernel QE support (drivers/soc/fsl/qe) already provides interface (examples) for configuring some of the QE subsystems (UCC slow, tdm, muram, also there is ucc_uart driver avilable) but there is no interface (example) for using UMCC.

So this specific question is related exactly to UMCC usage and current Kernel support availability.

It would be of help if any kind of PoC kernel driver, or configuration example in any other form is available beside

what is described in QE documentation.

Regards,

Aleksandar

Re: Linux Driver for QE UMCC

tedfriedl — Wed, 29 Nov 2017 21:20:53 GMT

Aleksandar,

How did you do with this project? I'm doing the same now for VxWorks. I think I have most of the UMCC/SI/TDM figured out for my application except for the commands to the UMCC through the CECR register. NXP's discussion about this in the Rev 8 QEIWRM is sparse and seems contradictory.

Ted Friedl