PowerQUICC Processors中的主题 MCC syncronization pattern, MPC8560 https://community.nxp.com/t5/PowerQUICC-Processors/MCC-syncronization-pattern-MPC8560/m-p/205585#M174 <HTML><HEAD></HEAD><BODY>Hello all!<BR /><BR />Did anyone set receive syncronization in MCC by pattern?<BR />(p. 33-15, MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual, Rev. 1)<BR /><BR />chamr = 0x7200, Transparent, Enabled pooling, SYNC=b10 (Receive - 8-bit, Transmit - none).<BR />zdstate = 0x00000000, because RCVSYNC = 0bxxxx_xxxx_xxxx_xxx1, Regular order.<BR />RCVSYNC = 0x9b - syncronization pattern.<BR />This results to no interrupt generation, I don't know why at the moment.</BODY></HTML> Thu, 06 Aug 2009 19:46:34 GMT gleb_itech 2009-08-06T19:46:34Z MCC syncronization pattern, MPC8560 https://community.nxp.com/t5/PowerQUICC-Processors/MCC-syncronization-pattern-MPC8560/m-p/205585#M174 <HTML><HEAD></HEAD><BODY>Hello all!<BR /><BR />Did anyone set receive syncronization in MCC by pattern?<BR />(p. 33-15, MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual, Rev. 1)<BR /><BR />chamr = 0x7200, Transparent, Enabled pooling, SYNC=b10 (Receive - 8-bit, Transmit - none).<BR />zdstate = 0x00000000, because RCVSYNC = 0bxxxx_xxxx_xxxx_xxx1, Regular order.<BR />RCVSYNC = 0x9b - syncronization pattern.<BR />This results to no interrupt generation, I don't know why at the moment.</BODY></HTML> Thu, 06 Aug 2009 19:46:34 GMT https://community.nxp.com/t5/PowerQUICC-Processors/MCC-syncronization-pattern-MPC8560/m-p/205585#M174 gleb_itech 2009-08-06T19:46:34Z