topic Re: MPC8306 : value of SRR0/SRR1 registers when MCP occurs in PowerQUICC Processors

MPC8306 : value of SRR0/SRR1 registers when MCP occurs

marie-claudemut — Mon, 20 Jun 2016 16:55:27 GMT

I am working on MCP exception due to TEA signal.

I use a Lauterbach tool in order to break onchip (at 0x200) when a MCP exception occurs and to list the value of SRR0/SRR1 registers

When an external interruption occurs during the timeout of ELBC (causing the TEA signal) , I cannot explain the following values of SRR0/SRR1 registers :

SRR0 = 0 and SRR1=0
SRR0 = 0X0500 and SRR1=0x41000

Is there somebody that has worked on this subject, and could give me an explanation.

Re: MPC8306 : value of SRR0/SRR1 registers when MCP occurs

marie-claudemut — Tue, 21 Jun 2016 10:40:07 GMT

I have an explication for 1) provided by LAUTERBACH

A software breakpoint clears SRR0/SRR1: it is a debugging restriction.

Re: MPC8306 : value of SRR0/SRR1 registers when MCP occurs

alexander_yakov — Thu, 23 Jun 2016 14:45:43 GMT

When Machine Check Interrupt exception is taken, SRR0 is loaded with the effective address of the next instruction in interrupted program stream, SRR1 is loaded with some flags indicating exception reason and some bits copied from MSR.

Note that analyzing effective address may be useless in some cases, because in some cases Machine Check interrupt may be caused by hardware reasons, but not because of executing incorrect instruction. For example - in case of data parity errors or cache parity errors.

Re: MPC8306 : value of SRR0/SRR1 registers when MCP occurs

marie-claudemut — Thu, 23 Jun 2016 17:27:56 GMT

I aggree with you: I only want to understand why the value of SRR0 and SRR1 seems to be related to current MSR and current EA of an External Interrupt processing ? and not related to the program instruction that accesses to an invalid address.

As I have written in the initial request "an interrupt occurs during the timeout of ELBC ".

In case of MCP, (refer to 5.5.2 of e300 Power architecture Core Family Reference Manual) the e300 does garantee that the machine check interrupt is always taken immediatly upon request, with a nonpredicted address saved in SRR0.

But nothing is specifically written on SRR1.

Re: MPC8306 : value of SRR0/SRR1 registers when MCP occurs

alexander_yakov — Fri, 01 Jul 2016 06:56:38 GMT

As I already said, MCP may be not related to program flow (that is - not caused by "program instruction that accesses to an invalid address")

For example if some hardware error happens on the bus (for example - TEA error) while the core is busy by another task (exception 0x500 in your example), than you may get MCP exception with context saving registers SRR0/SRR1 showing this 0x500 context, which is not related to actual reason of MCP.

Please keep in mind - core is not the only initiator of bus accesses, and even if the assess is initiated as a result of executing some core instruction, still it may be initiated by cache controller, by not by core itself.

Have a great day,
Alexander

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