<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>topic Re: MPC8315E PCIe memory configuration  in PowerQUICC Processors</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8315E-PCIe-memory-configuration/m-p/534236#M1548</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt; color: black;"&gt;Look at attached files. These files are documentation from NXP LTIB BSP for the MPC8315RDB board:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt; color: black;"&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fwww.nxp.com%2Fwebapp%2FDownload%3FcolCode%3DCWF-MPC8315E-RDB%26appType%3Dlicense%26location%3Dnull%26Parent_nodeId%3D1189462565666701466182%26Parent_pageType%3Dproduct%26Parent_nodeId%3D1189462565666701466182%26Parent_pageType%3Dproduct" rel="nofollow" target="_blank"&gt;https://www.nxp.com/webapp/Download?colCode=CWF-MPC8315E-RDB&amp;amp;appType=license&amp;amp;location=null&amp;amp;Parent_nodeId=1189462565666701466182&amp;amp;Parent_pageType=product&amp;amp;Parent_nodeId=1189462565666701466182&amp;amp;Parent_pageType=product&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt; color: black;"&gt;Use this documentation for PCIe setting on your board.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 04 Jul 2016 06:51:09 GMT</pubDate>
    <dc:creator>Pavel</dc:creator>
    <dc:date>2016-07-04T06:51:09Z</dc:date>
    <item>
      <title>MPC8315E PCIe memory configuration</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8315E-PCIe-memory-configuration/m-p/534235#M1547</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;SPAN style="color: #51626f; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif;"&gt;On physical hardware，PCIe 1 connects with PCI device（BCM56134）.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;SPAN style="color: #51626f; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif;"&gt;When during scanning pci 1 bus,why It can't detect bcm56134?&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;SPAN style="color: #51626f; font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif;"&gt;It print like this：&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_0.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/32905iFD87B278B472B204/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_0.png" alt="pastedImage_0.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;In fact,Should be printed like this:&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/32904iADD94825AC09E24B/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="154436_154436.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/121921i6CA1EA9EC5FA573D/image-size/large?v=v2&amp;amp;px=999" role="button" title="154436_154436.png" alt="154436_154436.png" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_3.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/33318i7D2551542C4593A9/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_3.png" alt="pastedImage_3.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;How to set the PCI configuration space, MEM space and&amp;nbsp; I/O space?&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;and Which register are need to set?&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;Such these Macro definitions,how to set ?&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;CONFIG_SYS_PCIE1_BASE、CONFIG_SYS_PCIE1_MEM_BASE、CONFIG_SYS_PCIE1_MEM_PHYS、CONFIG_SYS_PCIE1_MEM_SIZE?&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;CONFIG_SYS_PCIE1_CFG_BASE、CONFIG_SYS_PCIE1_CFG_SIZE?&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;CONFIG_SYS_PCIE1_IO_BASE、CONFIG_SYS_PCIE1_IO_PHYS、CONFIG_SYS_PCIE1_IO_SIZE?&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;=================================================================================&lt;/P&gt;&lt;P style="font-family: arial, helvetica, 'helvetica neue', verdana, sans-serif; color: #51626f;"&gt;&lt;SPAN style="color: #606060; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;SPAN style="color: #606060; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;/*&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;* General PCI&lt;/P&gt;&lt;P&gt;* Addresses are mapped 1-1.&lt;/P&gt;&lt;P&gt;*/&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCI_MEM_BASE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x80000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCI_MEM_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x10000000 /* 256M */&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCI_MMIO_BASE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x90000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCI_MMIO_PHYS&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CONFIG_SYS_PCI_MMIO_BASE&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCI_MMIO_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x10000000 /* 256M */&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCI_IO_BASE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCI_IO_PHYS&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0xE0300000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCI_IO_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00100000 /* 1M */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE1_BASE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0xb0000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE1_MEM_BASE 0xb0000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE1_MEM_PHYS 0xb0000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE1_MEM_SIZE&amp;nbsp;&amp;nbsp; 0x02000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE1_CFG_BASE 0xe0009000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE1_CFG_SIZE&amp;nbsp;&amp;nbsp; 0x00001000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE1_IO_BASE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE1_IO_PHYS&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0xb2000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE1_IO_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00800000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE2_BASE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0xb4000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE2_MEM_BASE&amp;nbsp; 0xb4000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE2_MEM_PHYS&amp;nbsp; 0xb4000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE2_MEM_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x02000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE2_CFG_BASE&amp;nbsp;&amp;nbsp; 0xe000a000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE2_CFG_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00001000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE2_IO_BASE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE2_IO_PHYS&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0xb6000000&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_PCIE2_IO_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x00800000&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Jul 2016 03:00:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8315E-PCIe-memory-configuration/m-p/534235#M1547</guid>
      <dc:creator>linjiepan</dc:creator>
      <dc:date>2016-07-04T03:00:17Z</dc:date>
    </item>
    <item>
      <title>Re: MPC8315E PCIe memory configuration</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8315E-PCIe-memory-configuration/m-p/534236#M1548</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt; color: black;"&gt;Look at attached files. These files are documentation from NXP LTIB BSP for the MPC8315RDB board:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt; color: black;"&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fwww.nxp.com%2Fwebapp%2FDownload%3FcolCode%3DCWF-MPC8315E-RDB%26appType%3Dlicense%26location%3Dnull%26Parent_nodeId%3D1189462565666701466182%26Parent_pageType%3Dproduct%26Parent_nodeId%3D1189462565666701466182%26Parent_pageType%3Dproduct" rel="nofollow" target="_blank"&gt;https://www.nxp.com/webapp/Download?colCode=CWF-MPC8315E-RDB&amp;amp;appType=license&amp;amp;location=null&amp;amp;Parent_nodeId=1189462565666701466182&amp;amp;Parent_pageType=product&amp;amp;Parent_nodeId=1189462565666701466182&amp;amp;Parent_pageType=product&lt;/A&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="font-size: 10.0pt; color: black;"&gt;Use this documentation for PCIe setting on your board.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Jul 2016 06:51:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8315E-PCIe-memory-configuration/m-p/534236#M1548</guid>
      <dc:creator>Pavel</dc:creator>
      <dc:date>2016-07-04T06:51:09Z</dc:date>
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