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    <title>topic [8555 ERM - L2 Cache - Initialisation] How to check whether cache is initialised by Core or by DMA Engine? in PowerQUICC Processors</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/8555-ERM-L2-Cache-Initialisation-How-to-check-whether-cache-is/m-p/506704#M1464</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;As per the Reference Manual of 8555, I wanted to know during the L2 cache Initialization:&lt;/P&gt;&lt;P&gt;1. How to check whether cache is initialized by core or by DMA engine?&lt;/P&gt;&lt;P&gt;2. In manual it states that ECC should be disabled if it is initialized by core else if it is DMA engine, ECC can be enabled(I am confused about this line in the reference manual)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Karunakar&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 28 Dec 2015 07:20:53 GMT</pubDate>
    <dc:creator>kaurnakarhv</dc:creator>
    <dc:date>2015-12-28T07:20:53Z</dc:date>
    <item>
      <title>[8555 ERM - L2 Cache - Initialisation] How to check whether cache is initialised by Core or by DMA Engine?</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/8555-ERM-L2-Cache-Initialisation-How-to-check-whether-cache-is/m-p/506704#M1464</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;As per the Reference Manual of 8555, I wanted to know during the L2 cache Initialization:&lt;/P&gt;&lt;P&gt;1. How to check whether cache is initialized by core or by DMA engine?&lt;/P&gt;&lt;P&gt;2. In manual it states that ECC should be disabled if it is initialized by core else if it is DMA engine, ECC can be enabled(I am confused about this line in the reference manual)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Karunakar&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Dec 2015 07:20:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/8555-ERM-L2-Cache-Initialisation-How-to-check-whether-cache-is/m-p/506704#M1464</guid>
      <dc:creator>kaurnakarhv</dc:creator>
      <dc:date>2015-12-28T07:20:53Z</dc:date>
    </item>
    <item>
      <title>Re: [8555 ERM - L2 Cache - Initialisation] How to check whether cache is initialised by Core or by DMA Engine?</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/8555-ERM-L2-Cache-Initialisation-How-to-check-whether-cache-is/m-p/506705#M1465</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The manual says that for case when L2 cache is configured as Memory-Mapped SRAM. Notice initialization should be made by software. So software designer decides how to initialize this memory. &lt;/P&gt;&lt;P&gt;* One way is execute software routine which fills this SRAM memory by the store instructions, i.e. initialize by core. Because in this case memory filled by sub-cache line transactions false ECC errors will be generated during the read-modify-write process. So software designer has to disable ECC error checking. &lt;/P&gt;&lt;P&gt;* The second way is programming DMA engine to write to this SRAM. For example we can move aligned cache-line size pattern from some memory to the SRAM. (For example we can move it from the NOR flash). In this case DMA engine uses cache-line writes; hence ECC checking can remain enabled during the initialization process.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 29 Dec 2015 07:23:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/8555-ERM-L2-Cache-Initialisation-How-to-check-whether-cache-is/m-p/506705#M1465</guid>
      <dc:creator>r8070z</dc:creator>
      <dc:date>2015-12-29T07:23:48Z</dc:date>
    </item>
    <item>
      <title>Re: [8555 ERM - L2 Cache - Initialisation] How to check whether cache is initialised by Core or by DMA Engine?</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/8555-ERM-L2-Cache-Initialisation-How-to-check-whether-cache-is/m-p/506706#M1466</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 30 Dec 2015 10:15:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/8555-ERM-L2-Cache-Initialisation-How-to-check-whether-cache-is/m-p/506706#M1466</guid>
      <dc:creator>kaurnakarhv</dc:creator>
      <dc:date>2015-12-30T10:15:24Z</dc:date>
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