topic MPC83xx 512MB DDR in PowerQUICC Processors

MPC83xx 512MB DDR

will_intelli — Wed, 06 Apr 2016 01:57:02 GMT

Hello,

I have a custom MPC8308-based board with 512MB of DDR RAM. I'm using two IBATs to configure the memory like this:

#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_IBAT0L   (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U   (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L   CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U   CONFIG_SYS_IBAT0U
#define CONFIG_SYS_IBAT1L   (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U   (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT1L   CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U   CONFIG_SYS_IBAT1U

U-boot is able to access the full 512MB, but when I go to boot Linux (3.18.17) it crashes with a "kernel paging request" error when I go to access >256MB of memory. It works fine when I only have 256MB configured. Has anyone had issues getting 512MB to work in Linux with a mpc83xx CPU before?

Will.

Re: MPC83xx 512MB DDR

Pavel — Wed, 06 Apr 2016 07:11:07 GMT

Your code contains the MPC8308 MMU configuration only.

Change also DDR setting. Find the CONFIG_DDR_SIZE. Change the MPC8308 DDR memory controller configuration.

Have a great day,
Pavel Chubakov

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Re: MPC83xx 512MB DDR

will_intelli — Wed, 06 Apr 2016 23:09:00 GMT

Hello,

These are my DDR settings, the 512MB of DDR is detected and accessible in u-boot. The issue I'm having is accessing it in all in Linux. I have written a test application to incrementally reserve memory which it is successfully doing from the top of memory (1FFFFFFFh) down. When it reaches around 10000000h after reserving 256MB I get a kernel paging request error. I see the same issue if I try to un-tar a large image into RAM.

#define CONFIG_SYS_DDR_SIZE 512 /* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
                | 0x00010000  /* ODT_WR to CSn */ \
                | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
                /* 0x80010202 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
                | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
                | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
                | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
                | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
                | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
                | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
                | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
                /* 0x00620802 */
#define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
                | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
                | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
                | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
                | (13 << TIMING_CFG1_REFREC_SHIFT ) \
                | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
                | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
                | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
                /* 0x3935d322 */
#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
                | ( 6 << TIMING_CFG2_CPO_SHIFT ) \
                | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
                | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
                | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
                | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
                | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
                /* 0x131088c8 */
#define CONFIG_SYS_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
                | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
                /* 0x03E00100 */
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
                | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
                /* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CONFIG_SYS_DDR_MODE2 0x00000000

Linux does think there is 512MB of RAM:

[root@mpc8308erdb /root]# cat /proc/iomem

00000000-1fffffff : System RAM

....

[root@mpc8308erdb /root]# top

Mem: 9996K used, 504744K free, 0K shrd, 3213780496K buff, 267200840K cached

....

Re: MPC83xx 512MB DDR

will_intelli — Thu, 07 Apr 2016 02:58:00 GMT

Hi,

I had my DDR configuration wrong and memory was aliasing at 256MB. This is the correct configuration:


#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
                | 0x00010000  /* ODT_WR to CSn */ \
                | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 | CSCONFIG_BANK_BIT_3
 )

Will.