topic DMA Configuration for DMA Engine 2 Direct Mode for MPC8306 in PowerQUICC Processors

DMA Configuration for DMA Engine 2 Direct Mode for MPC8306

manuelojea — Wed, 06 Apr 2016 13:18:55 GMT

We want to configure a DMA Direct Mode in the DMA engine 2.

I see in the MPC8306 Reference Manual for the register configuration, and I have a question regarding the DMAMR register.

The register DMAMR definition for the DRCNT is not clear. This bits is defined as "DMA request count. This field specifies the number of cache lines transferred per DMA request assertion".

We need to know the relationship between the definition of these bits with the DMA size value set in the register DMABCR.

For example, if we configura a 128 Byte DMA which value should be programed in the DMAMR[DRCNT].

Thank you in advance.

Re: DMA Configuration for DMA Engine 2 Direct Mode for MPC8306

Pavel — Thu, 07 Apr 2016 06:45:45 GMT

DRCNT specifies the number of cache lines transferred per DMA request assertion

If DRCNT=0b0101 then 32 bytes are transferred per DMA request.

BWC field determines how many data a given channel is allowed to transfer after it is granted access to the IOS interface and before it releases the interface to the next channel. This parameter doesn't allow a single channel to monopolize IOS.

The MPC8306 provides internal DMA request signals. This processor does not have external DMA request signal.

Values the DRCNT and BWC provide different IOS interface utilization and bus loading.

Set the DMAMR[DRCNT] to 4 cache lines if 128 bytes data transfers is needed.

Have a great day,
Pavel Chubakov

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Re: DMA Configuration for DMA Engine 2 Direct Mode for MPC8306

manuelojea — Thu, 07 Apr 2016 07:23:45 GMT

Thanks for your help.

I have another question:

The DMAMR[DRCNT] counter is limited to 1,2,4,8,16 and 32.

This means that DMA access can not be made of, for example, 160 bytes, because for this size the value in the register should be 5 cache lines.

In this case, we should configure the value in DMAMR[DRCNT] to 4 and the DMA engine mades to requests to transfer the 5 cache lines or we should configure to the next higher value to transfer 5 cache lines and then the DMA engine stops the accesses.

Regards.

Manuel Ojea