<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic MPC8270 PCI Bridge Configuration Register offset 0x40 and 0x98 in PowerQUICC Processors</title>
    <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8270-PCI-Bridge-Configuration-Register-offset-0x40-and-0x98/m-p/470254#M1344</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P class="MsoNormal"&gt;While making modifications to legacy software we have found writes to reserved/undocumented registers.&amp;nbsp; Maybe these are from an early datasheet or errata?&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;Both writes are to the host PCI configuration space (bus=0, dev=0, fxn=0)&lt;/P&gt;&lt;P class="MsoNormal"&gt;// PCI Bridge Option&lt;/P&gt;&lt;P class="MsoNormal"&gt;0x40 = 0x00000004;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;// PCI PIMOSA&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;0x98 = 0xC0000003;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;BR /&gt;Does anyone recognize what these register writes are doing?&lt;/P&gt;&lt;P class="MsoNormal"&gt;Thanks,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 22 Apr 2016 21:19:50 GMT</pubDate>
    <dc:creator>reedy</dc:creator>
    <dc:date>2016-04-22T21:19:50Z</dc:date>
    <item>
      <title>MPC8270 PCI Bridge Configuration Register offset 0x40 and 0x98</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8270-PCI-Bridge-Configuration-Register-offset-0x40-and-0x98/m-p/470254#M1344</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P class="MsoNormal"&gt;While making modifications to legacy software we have found writes to reserved/undocumented registers.&amp;nbsp; Maybe these are from an early datasheet or errata?&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;Both writes are to the host PCI configuration space (bus=0, dev=0, fxn=0)&lt;/P&gt;&lt;P class="MsoNormal"&gt;// PCI Bridge Option&lt;/P&gt;&lt;P class="MsoNormal"&gt;0x40 = 0x00000004;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;// PCI PIMOSA&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;0x98 = 0xC0000003;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;BR /&gt;Does anyone recognize what these register writes are doing?&lt;/P&gt;&lt;P class="MsoNormal"&gt;Thanks,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 22 Apr 2016 21:19:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8270-PCI-Bridge-Configuration-Register-offset-0x40-and-0x98/m-p/470254#M1344</guid>
      <dc:creator>reedy</dc:creator>
      <dc:date>2016-04-22T21:19:50Z</dc:date>
    </item>
    <item>
      <title>Re: MPC8270 PCI Bridge Configuration Register offset 0x40 and 0x98</title>
      <link>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8270-PCI-Bridge-Configuration-Register-offset-0x40-and-0x98/m-p/470255#M1345</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Those registers are definitely not from the MPC8270 PCI configuration space. If your software was really written for the MPC8270, you should remove those writes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Bulat&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 25 Apr 2016 11:03:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/PowerQUICC-Processors/MPC8270-PCI-Bridge-Configuration-Register-offset-0x40-and-0x98/m-p/470255#M1345</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2016-04-25T11:03:48Z</dc:date>
    </item>
  </channel>
</rss>

