mpc8306 DDR2 timing reg setup

go777 — Mon, 24 Aug 2015 04:12:42 GMT

mpc8306 ddr2 setup:

RCWLR = 0x4423_0086; input sys_clk = 33.333Mhz

so:

csb_clk = 133Mhz, DDR2_clk = 266Mhz

DDR2_tclk = 7.5ns

DDR2 Chip on MPC8306SOM is MT47H64M16HR-3,from micron's datasheet

tRP(min) = 15ns;

tRAS(min) = 40ns;

tRCD(min) = 15ns;

tRFC(min) = 127.5ns;

tWR(min) = 15ns;

tRCD(min) = 15ns;

tRRD(min) = 10ns;

tWTR(min) = 7.5ns;

by MPC8306 RefrenceManual:

DDR2_Timing_cfg_1_reg:

PRETOACT(tRP) = 15ns/7.5ns = 2;

ACTTOPRE(tRAS) = 40ns/7.5ns = 6;

ACTTORW(tRCD) = 15ns/7.5ns = 2;

CASLAT(CL) = 5; CL = 3 clocks;

REFREC(tRFC) = 127.5ns/7.5ns -8 = 9;

WRREC(tWR) = 15ns/7.5ns = 2;

ACTTOACT(tRRD) = 10ns/7.5ns = 2;

WRTORD(tWTR) = 7.5ns/7.5ns = 1;

so, value of DDR2_Timing_cfg_1 should be:

# TIMING_CONFIG_1

# bit 1-3 = 2 - PRETOACT precharge activate interval 3 clock cycles

# bit 4-7 = 6 - ACTTOPRE activate to precharge interval 9 clock cycles

# bit 9-11 = 2 = ACTTORW activate to r/w interval 3 clock cycles

# bit 13 - 15 = 5 - CASLAT CAS latency 3 clock cycles

# bit 16 - 19 = 9 - REFREC refresh recovery time 17 clock cycles

# bit 21 - 23 = 2 - WRREC data to precharge interval 3 clock cycles

# bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles

# bit 29 - 31 = 1 - WRTORD write data to read command interval 2 clock cycles

#reg ${DDR_CONT_GROUP}TIMING_CFG_1 = 0x26259221

actually,the mpc8306som_init.tcl

# TIMING_CONFIG_1

# bit 1-3 = 3 - PRETOACT precharge activate interval 3 clock cycles

# bit 4-7 = 9 - ACTTOPRE activate to precharge interval 9 clock cycles

# bit 9-11 = 3 = ACTTORW activate to r/w interval 3 clock cycles

# bit 13 - 15 = 5 - CASLAT CAS latency 3 clock cycles

# bit 16 - 19 = d - REFREC refresh recovery time 21 clock cycles

# bit 21 - 23 = 3 - WRREC data to precharge interval 3 clock cycles

# bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles

# bit 29 - 31 = 2 - WRTORD write data to read command interval 2 clock cycles

#reg ${DDR_CONT_GROUP}TIMING_CFG_1 = 0x3935d322

why?

the fact is use the value in mpc8306som_init.tcl is OK,use the value by calculate is wrong.

Have any suggestiton?

Re: mpc8306 DDR2 timing reg setup

Bulat — Mon, 24 Aug 2015 13:25:58 GMT

It is possible that the problem happens due to WRTORD value, try to set it to 2.

We recommend that WRTORD value were set to 2 minimum, even if it is 1 as per SDRAM datasheet. See AN3369 app note for details.

Regards,

Bulat

topic mpc8306 DDR2 timing reg setup in PowerQUICC Processors

mpc8306 DDR2 timing reg setup

Re: mpc8306 DDR2 timing reg setup