PowerQUICC ProcessorsのトピックeTSEC1-RGMII and eTSEC2-MII in MPC8308

eTSEC1-RGMII and eTSEC2-MII in MPC8308

venkateshn — Thu, 03 Sep 2015 10:43:06 GMT

Hi,

In MPC8308 processor i am using eTSEC1 in RGMII mode and eTSEC2 in MII mode,

In MII mode i have two clarifications,

1) i have connected TSEC2_GTX_CLK pin to ground through 1K resistor but in datasheet it is mentioned like This signal feeds back the uninverted transmit clock in MII mode in Detailed Signal Descriptionsso and i gone through the Design Checklist there it is clearly mentioned like it is not used in MII mode.

2) TSECn_TX_ER this pin in eTSEC1 used as a configuration ECC pin where as in MII mode it suggested to connect to PHY but this pin is not there in the PHY having Part Number KSZ8041NL from MIcrel so kindly check the need of this signal and kindly share me any reference design which has got MII mode in this series of processors(eTSEC).

3) TSEC2_TX_CLK i have connected this pin to TX_CLK pin of PHY.

Re: eTSEC1-RGMII and eTSEC2-MII in MPC8308

r8070z — Thu, 03 Sep 2015 15:47:48 GMT

Have a great day,

1) Yes TSEC2_GTX_CLK is not required for MII interface.

2) According to MII specifications TX_ER (MAC to PHY Transmit error) is an optional signal. PHY’s TX_ER input allows the system MAC to force PHY to deliberately corrupt the transmitted packet. A similar function can be accomplished by having the MAC signal the PHY to stop transmission mid-packet. Since the function of aborting a transmit packet is more easily attained with the latter method, the TX_ER pin may be not implement by PHY.

3) Yes in MII mode TSEC2_TX_CLK pin is input for transmit clock that provides a timing reference for the TSECn_TX_EN, TSECn_TXD signals.

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Re: eTSEC1-RGMII and eTSEC2-MII in MPC8308

venkateshn — Fri, 04 Sep 2015 05:05:00 GMT

r8070z,

Thanks for your replay,

with reference to point no.1 TSEC2_GTX_CLK in the above post please clarify me the below query,

For TSEC2_GTX_CLK it is mentioned in datasheet like This signal feeds back the uninverted transmit clock in MII mode if we are not used this signal in MII mode why they have included above description.

Re: eTSEC1-RGMII and eTSEC2-MII in MPC8308

r8070z — Thu, 10 Sep 2015 15:52:11 GMT

I do not know why they wrote that. I think just for information. In any case because in MII mode this pin is an output and do not required for MII so it can be left open.

Re: eTSEC1-RGMII and eTSEC2-MII in MPC8308

venkateshn — Fri, 11 Sep 2015 11:42:02 GMT

Hi,

Thanks for your kind replay,

I have following clarification on layer stack up for MPC8308 processor,

I am going for 8 layer PCB and the stack up is as shown below,

Layer Number

Layer Name

Material Type

Top

Dielectric

Conductive

GND1

Dielectric

Conductive

Sig1

Dielectric

Conductive

Sig2

Dielectric

Conductive

PWR

Dielectric

Conductive

Sig3

Dielectric

Conductive

GND2

Dielectric

Conductive

Bottom

Dielectric

Conductive

Kindly check the reference which I considered is ok r not, waiting for your early replay.

Regards,

Venkatesh N