Processor Expert SoftwareのトピックRe: Kinetis SPI Master Clock Polarity after Init

Kinetis SPI Master Clock Polarity after Init

Vagni — Thu, 16 Feb 2012 16:40:53 GMT

I am developing my application on Kinetis K60 with CodeWarrior 10.1 with ProcessorExpert 5.1 and MQX 3.7.

I need to drive an SPI bus in master mode, so I use the SPIMaster_LDD embedded component.

I initialize clock polarity as HIGH and clock phase as CHANGE ON LEADING EDGE.

But after the execution of the SPI_Init() function the CLK pin is at LOW level. Why? The clock line idle state should be high.

For this reason, my first SPI Master transaction to the slave device (which requires a high clock idle state) always fails.

However, after the first SPI transaction the CLK pin remains high, so all the subsequent SPI transactions are good.

As a workaround, I make a dummy SPI transaction of a single data byte after the SPI_Init() function call and then I can get all the real subsequent transactions to work properly.

Does the Kinetis SPI peripheral initialization make the CLK pin output the correct idle level set by the chosen clock polarity?

Re: Kinetis SPI Master Clock Polarity after Init

ProcessorExpert — Fri, 17 Feb 2012 01:32:55 GMT

Hello,

I am not aware of such problem in SPIMaster_LDD component. Could you please provide the ProcessorExpert.pe file from your project in order to analayze it?

best regards
Vojtech Filip
Processor Expert Support Team

Re: Kinetis SPI Master Clock Polarity after Init

Vagni — Fri, 17 Feb 2012 01:45:27 GMT

Hello Filip,

See my attached ProcessorExpert.pe file.

Thank you.

Re: Kinetis SPI Master Clock Polarity after Init

ProcessorExpert — Mon, 20 Feb 2012 17:27:18 GMT

Hello,

I have discussed the problem with developers and the behaviour of SPIMaster_LDD i correct and correspond to the description of DSPI device in reference manual (RM).

The parameters of the communuicaiton are set during data transfer. For more details please see section: "49.3.7 DSPI PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)" in RM.

So, it seems your workaround was correct.

best regards
Vojtech Filip
Processor Expert Support Team

Re: Kinetis SPI Master Clock Polarity after Init

sgraves — Sun, 18 Dec 2016 23:50:12 GMT

Even though this thread is long dead, I would like to correct the information in threads like these for those who are googling for solutions to various problems. So this comment is for future googlers, not the original participants.

This thread demonstrates an often confused understanding of the clock polarity settings. If the clock setting is active high then it will idle low. So the clock was behaving correctly for the chosen setting. If one wants an idle high and clocking on the rising edge (a very common SPI configuration) then the choices should be ACTIVE LOW and CLOCK ON SECOND EDGE.