topic Re: MIPI DSI single data lane display on imx8mp in Processor Expert Software

MIPI DSI single data lane display on imx8mp

vprajapati — Tue, 21 Jan 2025 12:00:58 GMT

I am working on a project where, I need to interface a ILI9488 MIPI DSI display. It is single lane mipi dsi display having resolution of 320x480 pixels. It supports 16 bit, 18 bit and 24b bit color formats.

The init sequence is provided by display manufacturer and well proven on their side.
I am facing an issue that we are getting white screen only on the display. No other data, no single dot or no single line. There are no any errors in driver probbing and in enable panel.

I have another 5" LCD, with 4 lane mipi-dsi, it is working well with the same hardware.

I would like to know if is there any bug on the NXP MIPI driver side for single lane MIPI DSI ?

I am using Yocto Scarthgap 6.6.23 for my bringup.

Thanks

Re: MIPI DSI single data lane display on imx8mp

Bio_TICFSL — Wed, 22 Jan 2025 14:36:52 GMT

Hello,

You need at least 2 lanes to use the MIPI DSI on the MX8MP one single data lane does not work because it is necessary to patch the file drivers/gpu/drm/bridge/nwl-dsi.c

The function nwl_dsi_bridge_atomic_check makes lanes=1 not a choice

if (config->lanes < 2 || config->lanes > 4)
return -EINVAL;

With "(config->lanes < 1" the function continues executing.

Regards

Re: MIPI DSI single data lane display on imx8mp

vprajapati — Wed, 22 Jan 2025 14:43:15 GMT

Can you please share the patch for single MIPI DSI lanes to make it functional? @Bio_TICFSL

Re: MIPI DSI single data lane display on imx8mp

Bio_TICFSL — Wed, 22 Jan 2025 14:53:24 GMT

Hello,

There is no patch I mentioned the line that need to be patch, the developer are working on this, but there is no patch so far.

Regards

Re: MIPI DSI single data lane display on imx8mp

vprajapati — Wed, 22 Jan 2025 15:12:14 GMT

@Bio_TICFSL

There is no such condition like you "config->lanes < 2" anywhere in nwl_dsi_bridge_atomic_check. Not anywhere else as well.

static int nwl_dsi_bridge_atomic_check(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,
struct drm_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
struct nwl_dsi *dsi = bridge_to_dsi(bridge);
struct drm_display_mode *adjusted = &crtc_state->adjusted_mode;

if (!dsi->use_dcss && !dsi->pdata->use_dcnano_or_epdc) {
/* At least LCDIF + NWL needs active high sync */
adjusted->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
adjusted->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
} else {
adjusted->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
adjusted->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
}

return 0;
}

I am using Linux 6.6.23. Can you please check again.

Re: MIPI DSI single data lane display on imx8mp

vprajapati — Thu, 23 Jan 2025 10:07:51 GMT

Hi @Bio_TICFSL

I am working on imx8mp and it has Linux 6.6.23.

It is using drivers/gpu/drm/bridge/sec-dsim.c for mipi dsi. It has no condition like you mwntioned earlier.

Re: MIPI DSI single data lane display on imx8mp

vprajapati — Wed, 29 Jan 2025 02:06:50 GMT

Hi @Bio_TICFSL,

We have verified that single data lane is being used in sec-dsim.c.

The same issue still persist. Can you please help me ?