SPI Communication Issue with DSPI_MasterTransferBlocking on MK10DN512VLK10

Jagdish837 — Wed, 22 Jan 2025 07:16:01 GMT

Hello ,

I am working on SPI communication between an MK10DN512VLK10 IPMC (SPI master) and an Artix FPGA (SPI slave). The project uses the SDK SDK_2_2_0_MK10DN512VLK10 and DSPI driver.

Configuration details:

DSPI_MASTER_BASEADDR :- SPI1

DSPI_MASTER_PCS_FOR_INIT :- kDSPI_Pcs0

DSPI_MASTER_PCS_FOR_TRANSFER :- kDSPI_MasterPcs0

CPOL :- kDSPI_ClockPolarityActiveLow

CPHA :- kDSPI_ClockPhaseSecondEdge

Bit order :- kDSPI_MsbFirst

PCS :- ActiveLow

Issue Summary:

When transferring a single byte of data using DSPI_MasterTransferBlocking, the communication works perfectly. However, when transferring two or more bytes of data, the communication fails. The SPI slave (FPGA) does not receive the correct data, and the master side reads all ones in the received data.

Code Snippet:

void IPMC_Write_Artix()

{

masterTestData[0] = 0xA5;

masterTestData[1] = 0xA5;

/* Start master transfer, send data to slave */

masterXfer.txData = masterTestData;

masterXfer.rxData = NULL;

masterXfer.dataSize = 2;

masterXfer.configFlags = kDSPI_MasterCtar1 | EXAMPLE_DSPI_MASTER_PCS_FOR_TRANSFER | kDSPI_MasterPcsContinuous;

/* Perform SPI blocking transfer */

Status = DSPI_MasterTransferBlocking(EXAMPLE_DSPI_MASTER_BASEADDR, &masterXfer);

if (Status == kStatus_Success)

{

PRINTF("Successfully send data from master.\r\n");

}

else

{

PRINTF("Error send data from master: %d\r\n", Status);

}

Please help on this

Thanks

Jagdish Gorain

Re: SPI Communication Issue with DSPI_MasterTransferBlocking on MK10DN512VLK10

Joey_z — Thu, 06 Feb 2025 03:51:37 GMT

Hi,Jagdish837

Thank you for contacting us.

According to the RM of MK10DN512VLK10, SPI frames longer than 16 bits can be supported using the continuous selection format, make sure your MK10DN512VLK10 using the continuous selection format when you send more bytes of data using SPI.

In addition ,Check the configuration on the FPGA side. Since single-byte transfers work correctly but multi-byte transfers fail, this may indicate an issue with how the FPGA handles multi-byte transfers. Ensure that the SPI slave configuration on the FPGA supports multi-byte transfers.

Joey

Processor Expert Software中的主题 SPI Communication Issue with DSPI_MasterTransferBlocking on MK10DN512VLK10

SPI Communication Issue with DSPI_MasterTransferBlocking on MK10DN512VLK10

Issue Summary:

Re: SPI Communication Issue with DSPI_MasterTransferBlocking on MK10DN512VLK10