<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Processor Expert SoftwareのトピックRe: [T2080RDB] How to configure Common clock for PCIe endpoint</title>
    <link>https://community.nxp.com/t5/Processor-Expert-Software/T2080RDB-How-to-configure-Common-clock-for-PCIe-endpoint/m-p/1930881#M5846</link>
    <description>&lt;P&gt;&lt;SPAN&gt;You can change the link control register in drivers/pci/fsl_pci_init.c&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;for ex as below to change cc to 1:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;pci_lcr = pcie_cap_pos + 0x10;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;temp32 |= 0x40; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 13 Aug 2024 07:20:15 GMT</pubDate>
    <dc:creator>yipingwang</dc:creator>
    <dc:date>2024-08-13T07:20:15Z</dc:date>
    <item>
      <title>[T2080RDB] How to configure Common clock for PCIe endpoint</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/T2080RDB-How-to-configure-Common-clock-for-PCIe-endpoint/m-p/1924437#M5837</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We are working on&lt;SPAN&gt;&amp;nbsp;T2080&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;PCIe . According to QorIQ_T2080_Reference_Manual(PgNo : 1545) we want to change the&amp;nbsp;Common clock configuration(CCC) bit value in Link Control Register.&lt;/P&gt;&lt;P&gt;Can I get&amp;nbsp; more information on how to configure it in U-boot level?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-center" image-alt="image.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/291796i668CD8185FF8C188/image-size/medium?v=v2&amp;amp;px=400" role="button" title="image.png" alt="image.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Thanks and Regards,&lt;/P&gt;&lt;P&gt;Venkat Vellanki.&lt;/P&gt;</description>
      <pubDate>Sat, 03 Aug 2024 16:33:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/T2080RDB-How-to-configure-Common-clock-for-PCIe-endpoint/m-p/1924437#M5837</guid>
      <dc:creator>Venkat_Vellanki</dc:creator>
      <dc:date>2024-08-03T16:33:39Z</dc:date>
    </item>
    <item>
      <title>Re: [T2080RDB] How to configure Common clock for PCIe endpoint</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/T2080RDB-How-to-configure-Common-clock-for-PCIe-endpoint/m-p/1929971#M5843</link>
      <description>&lt;P&gt;Discussing with the AE team.&lt;/P&gt;</description>
      <pubDate>Mon, 12 Aug 2024 07:30:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/T2080RDB-How-to-configure-Common-clock-for-PCIe-endpoint/m-p/1929971#M5843</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2024-08-12T07:30:42Z</dc:date>
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    <item>
      <title>Re: [T2080RDB] How to configure Common clock for PCIe endpoint</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/T2080RDB-How-to-configure-Common-clock-for-PCIe-endpoint/m-p/1930881#M5846</link>
      <description>&lt;P&gt;&lt;SPAN&gt;You can change the link control register in drivers/pci/fsl_pci_init.c&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;for ex as below to change cc to 1:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;pci_lcr = pcie_cap_pos + 0x10;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;temp32 |= 0x40; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 13 Aug 2024 07:20:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/T2080RDB-How-to-configure-Common-clock-for-PCIe-endpoint/m-p/1930881#M5846</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2024-08-13T07:20:15Z</dc:date>
    </item>
    <item>
      <title>Re: [T2080RDB] How to configure Common clock for PCIe endpoint</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/T2080RDB-How-to-configure-Common-clock-for-PCIe-endpoint/m-p/1931024#M5847</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;A href="https://community.nxp.com/t5/user/viewprofilepage/user-id/52411" target="_self"&gt;&lt;SPAN class=""&gt;yipingwang&amp;nbsp; ,&lt;/SPAN&gt;&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class=""&gt;Thanks for the response&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;We have already changed as mentioned above but still couldn't configure to common clock.&lt;/P&gt;&lt;P&gt;We configured in the following path /drivers/pci/fsl_pci_init.c&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;&lt;EM&gt;void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;{&lt;/EM&gt;&lt;BR /&gt;&lt;I&gt;#code&lt;/I&gt;&lt;BR /&gt;&lt;EM&gt;if (retrain_link_g)&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;{&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;pci_lcr = pcie_cap_pos + 0x10;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;temp32 = 0;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;pci_hose_read_config_dword(hose, dev, pci_lcr, &amp;amp;temp32);&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;printf("pci_lcr: 0x%x\n", temp32);&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;temp32 |= 0x40;&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;printf("pci_lcr mk: 0x%x\n", temp32);&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;udelay(100000);&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;}&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;}&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Are there any other modifications that are required.?&lt;/P&gt;</description>
      <pubDate>Tue, 13 Aug 2024 09:46:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/T2080RDB-How-to-configure-Common-clock-for-PCIe-endpoint/m-p/1931024#M5847</guid>
      <dc:creator>Venkat_Vellanki</dc:creator>
      <dc:date>2024-08-13T09:46:09Z</dc:date>
    </item>
    <item>
      <title>Re: [T2080RDB] How to configure Common clock for PCIe endpoint</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/T2080RDB-How-to-configure-Common-clock-for-PCIe-endpoint/m-p/1973211#M5851</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/52411"&gt;@yipingwang&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please let us know any update on this as soon as possible .&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Venkat Velanki.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 14 Oct 2024 09:16:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/T2080RDB-How-to-configure-Common-clock-for-PCIe-endpoint/m-p/1973211#M5851</guid>
      <dc:creator>Venkat_Vellanki</dc:creator>
      <dc:date>2024-10-14T09:16:02Z</dc:date>
    </item>
    <item>
      <title>Re: [T2080RDB] How to configure Common clock for PCIe endpoint</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/T2080RDB-How-to-configure-Common-clock-for-PCIe-endpoint/m-p/1973229#M5853</link>
      <description>&lt;P&gt;Please refer to the following update from the AE team.&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;No further information from software team since it is an old part with old SDK.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;customer may search the source code and find a better way on their own.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 14 Oct 2024 09:33:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/T2080RDB-How-to-configure-Common-clock-for-PCIe-endpoint/m-p/1973229#M5853</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2024-10-14T09:33:53Z</dc:date>
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  </channel>
</rss>

