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    <title>topic Regarding PORT_POL and PORT_ENA registers in Processor Expert Software</title>
    <link>https://community.nxp.com/t5/Processor-Expert-Software/Regarding-PORT-POL-and-PORT-ENA-registers/m-p/1284743#M4721</link>
    <description>&lt;P&gt;What is the use of port-wise PORT_POLx and PORT_ENAx register, already we have different base address for the two GINT ports. What does it mean when we use GINT1_BASE-&amp;gt;PORT_ENA[0]?&lt;/P&gt;</description>
    <pubDate>Mon, 31 May 2021 10:58:06 GMT</pubDate>
    <dc:creator>Amar1</dc:creator>
    <dc:date>2021-05-31T10:58:06Z</dc:date>
    <item>
      <title>Regarding PORT_POL and PORT_ENA registers</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/Regarding-PORT-POL-and-PORT-ENA-registers/m-p/1284743#M4721</link>
      <description>&lt;P&gt;What is the use of port-wise PORT_POLx and PORT_ENAx register, already we have different base address for the two GINT ports. What does it mean when we use GINT1_BASE-&amp;gt;PORT_ENA[0]?&lt;/P&gt;</description>
      <pubDate>Mon, 31 May 2021 10:58:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/Regarding-PORT-POL-and-PORT-ENA-registers/m-p/1284743#M4721</guid>
      <dc:creator>Amar1</dc:creator>
      <dc:date>2021-05-31T10:58:06Z</dc:date>
    </item>
    <item>
      <title>Re: Regarding PORT_POL and PORT_ENA registers</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/Regarding-PORT-POL-and-PORT-ENA-registers/m-p/1284872#M4722</link>
      <description>&lt;P&gt;Hello &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/187054"&gt;@Amar1&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;PORT_POLx register states the polarity of the pins in port “x” that will activate an interrupt. The PORT_ENAx register dictates which pins of the port will be enabled for an interruption and which won’t.&lt;/P&gt;
&lt;P&gt;So, with GINT1_BASE-&amp;gt;PORT_ENA[0], you are referring to the enable register of Port 0 with the Peripheral GINT1 base address. Here, you would assign a number based on the pins that you would like enabled for the interrupt.&lt;/P&gt;
&lt;P&gt;If you would like more information about the polarity and enable registers, please refer to Chapter 21 of the User Manual (p. 398). Here’s the download link:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=UM11126" target="_blank"&gt;https://www.nxp.com/webapp/Download?colCode=UM11126&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Also, you can find a GINT example on the SDK of your board of choice, under “driver_examples”.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Edwin.&lt;/P&gt;</description>
      <pubDate>Mon, 31 May 2021 16:02:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/Regarding-PORT-POL-and-PORT-ENA-registers/m-p/1284872#M4722</guid>
      <dc:creator>EdwinHz</dc:creator>
      <dc:date>2021-05-31T16:02:25Z</dc:date>
    </item>
    <item>
      <title>Re: Regarding PORT_POL and PORT_ENA registers</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/Regarding-PORT-POL-and-PORT-ENA-registers/m-p/1289000#M4727</link>
      <description>&lt;P&gt;Thanks Edwin,&lt;/P&gt;&lt;P&gt;Got it and GINT is working fine.&lt;/P&gt;</description>
      <pubDate>Tue, 08 Jun 2021 09:36:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/Regarding-PORT-POL-and-PORT-ENA-registers/m-p/1289000#M4727</guid>
      <dc:creator>Amar1</dc:creator>
      <dc:date>2021-06-08T09:36:51Z</dc:date>
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