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    <title>Processor Expert SoftwareのトピックRe: Memory protection Unit (MPU) for Non-Volatile memory for S32G274</title>
    <link>https://community.nxp.com/t5/Processor-Expert-Software/Memory-protection-Unit-MPU-for-Non-Volatile-memory-for-S32G274/m-p/1098778#M4516</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Vinod,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;To answer your question on memory protection configurations for external flash (QuadSPI NOR flash), please have my input:&lt;/P&gt;&lt;P&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;[Vinod] I need to understand, is it possible to implement Memory Protection Unit for external NOR flash&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;(MX25UW512) IC ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;[Ajesh] Yes, it is possible to protect memory addresses of external flash using XRDC MRC7 configurations. Please refer MRGD register offset for MRC7 configurations for protection of flash addresses.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/108845iCCA36544DBBC0868/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;[Vinod] If NOT, then for implementing MPU which memory do I need to consider other than SRAM&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;and external NOR ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;[Ajesh] There are protection available using XRDC for all volatile and non-volatile memories using XRDC MRC configuriatons. I have put a snapshot from RM XRDC MRC configuration information below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/108846i6005CFB9E629D28D/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;[Vinod] If I consider external DRAM in place of NOR Flash IC (MX25UW512), How can I store our application&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;code in DRAM region and execute from there ?&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;Do I need to do initialization for DRAM during code startup and in Linker file (.ld) I shall map memory section at DRAM address (0x60000000) , will it be ok?&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;[Ajesh] You can execute your application from any of the memory SRAM/Flash/DRAM, to execute from a specific memory you need to build your application for those addresses by mentioning in linker file with start address.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;For DRAM address, as per memory map CM7_0 access DRAM at 0x60000000 and other masters access DRAM at 0x80000000.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;Ajesh&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 02 Jun 2020 06:50:48 GMT</pubDate>
    <dc:creator>AjeshKumar</dc:creator>
    <dc:date>2020-06-02T06:50:48Z</dc:date>
    <item>
      <title>Memory protection Unit (MPU) for Non-Volatile memory for S32G274</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/Memory-protection-Unit-MPU-for-Non-Volatile-memory-for-S32G274/m-p/1098777#M4515</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN&gt;I have few question about controller S32G274A about MPU as below :&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;UL style="margin-top: 0cm;"&gt;&lt;LI style="color: #002060; margin-left: 0cm;"&gt;&lt;SPAN&gt;In my current implementation all memory section(.text, .data, .bss, etc) are mapped in to SRAM area&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;SPAN&gt;(0x34000000). &lt;/SPAN&gt;&lt;/P&gt;&lt;UL style="margin-top: 0cm;"&gt;&lt;LI style="color: #002060; margin-left: 0cm;"&gt;&lt;SPAN&gt;As SRAM is volatile memory, after compilation we are generating binary file for application code and &lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;SPAN&gt;flash it to NOR Flash IC (MX25UW512) and execute from NOR flash. In this way we store application &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;code in to NON volatile memory. &lt;/SPAN&gt;&lt;/P&gt;&lt;UL style="margin-top: 0cm;"&gt;&lt;LI style="color: #002060; margin-left: 0cm;"&gt;&lt;SPAN&gt;I need to understand, is it possible to implement Memory Protection Unit for external NOR flash&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;SPAN&gt;(MX25UW512) IC ?&lt;/SPAN&gt;&lt;/P&gt;&lt;UL style="margin-top: 0cm;"&gt;&lt;LI style="color: #002060; margin-left: 0cm;"&gt;&lt;SPAN&gt;If NOT, then for implementing MPU which memory do I need to consider other than SRAM &lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;SPAN&gt;and external NOR ?&lt;/SPAN&gt;&lt;/P&gt;&lt;UL style="margin-top: 0cm;"&gt;&lt;LI style="color: #002060; margin-left: 0cm;"&gt;&lt;SPAN&gt;If I consider external DRAM in place of NOR Flash IC (MX25UW512), How can I store our application &lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;SPAN&gt;code in DRAM region and execute from there ?&lt;/SPAN&gt;&lt;/P&gt;&lt;UL style="margin-top: 0cm;"&gt;&lt;LI style="color: #002060; margin-left: 0cm;"&gt;&lt;SPAN&gt;Do I need to do initialization for DRAM during code startup and in Linker file (.ld) I shall map memory section at DRAM address (0x60000000) , will it be ok?&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;My basic objective is to implement Memory protection Unit for Non Volatile memory for S32G274. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Any input in this context is highly appreciated. &lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 May 2020 14:35:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/Memory-protection-Unit-MPU-for-Non-Volatile-memory-for-S32G274/m-p/1098777#M4515</guid>
      <dc:creator>vinod_bargaje</dc:creator>
      <dc:date>2020-05-04T14:35:15Z</dc:date>
    </item>
    <item>
      <title>Re: Memory protection Unit (MPU) for Non-Volatile memory for S32G274</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/Memory-protection-Unit-MPU-for-Non-Volatile-memory-for-S32G274/m-p/1098778#M4516</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Vinod,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;To answer your question on memory protection configurations for external flash (QuadSPI NOR flash), please have my input:&lt;/P&gt;&lt;P&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;[Vinod] I need to understand, is it possible to implement Memory Protection Unit for external NOR flash&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;(MX25UW512) IC ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;[Ajesh] Yes, it is possible to protect memory addresses of external flash using XRDC MRC7 configurations. Please refer MRGD register offset for MRC7 configurations for protection of flash addresses.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/108845iCCA36544DBBC0868/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;[Vinod] If NOT, then for implementing MPU which memory do I need to consider other than SRAM&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;and external NOR ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;[Ajesh] There are protection available using XRDC for all volatile and non-volatile memories using XRDC MRC configuriatons. I have put a snapshot from RM XRDC MRC configuration information below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/108846i6005CFB9E629D28D/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;[Vinod] If I consider external DRAM in place of NOR Flash IC (MX25UW512), How can I store our application&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;code in DRAM region and execute from there ?&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;Do I need to do initialization for DRAM during code startup and in Linker file (.ld) I shall map memory section at DRAM address (0x60000000) , will it be ok?&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;[Ajesh] You can execute your application from any of the memory SRAM/Flash/DRAM, to execute from a specific memory you need to build your application for those addresses by mentioning in linker file with start address.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;For DRAM address, as per memory map CM7_0 access DRAM at 0x60000000 and other masters access DRAM at 0x80000000.&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;Ajesh&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 Jun 2020 06:50:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/Memory-protection-Unit-MPU-for-Non-Volatile-memory-for-S32G274/m-p/1098778#M4516</guid>
      <dc:creator>AjeshKumar</dc:creator>
      <dc:date>2020-06-02T06:50:48Z</dc:date>
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