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    <title>Processor Expert SoftwareのトピックRe: Setting S12ZVLA128 VDD Level</title>
    <link>https://community.nxp.com/t5/Processor-Expert-Software/Setting-S12ZVLA128-VDD-Level/m-p/812163#M4193</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have the same issue.&amp;nbsp; You can changed it in Cpu.c , but when you complied the project next time,It will become default by PE. It looks like PE's bug&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 03 May 2019 06:09:35 GMT</pubDate>
    <dc:creator>pingwang</dc:creator>
    <dc:date>2019-05-03T06:09:35Z</dc:date>
    <item>
      <title>Setting S12ZVLA128 VDD Level</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/Setting-S12ZVLA128-VDD-Level/m-p/812162#M4192</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;VDD on this uC is defaulted to 3.3V.&amp;nbsp; To switch it to 5V there is a bit in the&amp;nbsp;CPMUVREGCTL register.&amp;nbsp; Processor Expert provides the ability to set all other editable bits in this register through it's standard interface, but not that one.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I ended up putting the following in my main() routine:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: courier new,courier,monospace;"&gt;// Change VREG from 3.3V (default) to 5V&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: courier new,courier,monospace;"&gt;setReg8Bits(CPMUVREGCTL, 0x80);&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This works perfectly when I am debugging, but as soon as I power cycle the module everything else works but VDD is still at 3.3V.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;Is there some way I am missing to do this properly through Processor Expert or is this just something that fell through the cracks on NXP's part?&lt;/LI&gt;&lt;LI&gt;Why does this work while debugging, but not when running independently?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 19 Oct 2018 13:47:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/Setting-S12ZVLA128-VDD-Level/m-p/812162#M4192</guid>
      <dc:creator>bigtwisty</dc:creator>
      <dc:date>2018-10-19T13:47:44Z</dc:date>
    </item>
    <item>
      <title>Re: Setting S12ZVLA128 VDD Level</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/Setting-S12ZVLA128-VDD-Level/m-p/812163#M4193</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have the same issue.&amp;nbsp; You can changed it in Cpu.c , but when you complied the project next time,It will become default by PE. It looks like PE's bug&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 May 2019 06:09:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/Setting-S12ZVLA128-VDD-Level/m-p/812163#M4193</guid>
      <dc:creator>pingwang</dc:creator>
      <dc:date>2019-05-03T06:09:35Z</dc:date>
    </item>
    <item>
      <title>Re: Setting S12ZVLA128 VDD Level</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/Setting-S12ZVLA128-VDD-Level/m-p/812164#M4194</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I found in the RM that this pin is Write Once in normal mode.&amp;nbsp; If you write it once before you initialize PE it will work in normal mode because PE will be unable to override the value.&amp;nbsp; If you also write it after you initialize PE it will override the PE settings when debugging.&amp;nbsp; You need to ensure you write the entire register correctly however, as PE will be unable to write the register again in normal mode.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 May 2019 14:13:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/Setting-S12ZVLA128-VDD-Level/m-p/812164#M4194</guid>
      <dc:creator>bigtwisty</dc:creator>
      <dc:date>2019-05-14T14:13:50Z</dc:date>
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