topic Re: I2S time slots and DMA buffers in Processor Expert Software

I2S time slots and DMA buffers

future_boston — Wed, 06 Jun 2012 03:06:01 GMT

I want to use the DMA controller with the I2S interface (now the SAI on the 120MHz Kinetis K60). When I go to setup a DMA channel with PE, it allows me to define the number of time slots but only one buffer to transmit or receive from.

It would seem that if the DMA channel could split up the time slots, it would require X number of buffers for X number of time slots but I don’t see any capability to set up this buffer structure. Can PE arrange to DMA time slots to separate buffers?

Re: I2S time slots and DMA buffers

jiri_rezler — Mon, 24 Sep 2012 08:46:15 GMT

Hello

The SAI device (on the Kinetis 120MHz) does not allow division of “Time slots” data stream.
Data frames (x frames) are stored in a one data stream buffer. Data arrangement in the data buffer is dependent on the sequence transmission "Time slots" 0,1,2,... in frame.
For a I2S codec are used only 2 time slots (0,1) and data arrangement in buffer is

Slot:   0                       1
LeftChannel, RightCHannel,    // Sample 0
LeftChannel, RightCHannel,    // Sample 1
LeftChannel, RightCHannel,    // Sample 2
LeftChannel, RightCHannel,    // Sample 3
...
LeftChannel, RightCHannel,    // Sample n

=> Buffer arrangement: uint16_t Buffer[2][SampleNum]; // first index: 0 = LeftChannel, 1= RightChanne

Re: I2S time slots and DMA buffers

egoodii — Tue, 02 Jul 2013 00:18:12 GMT

I know I am ridiculously late to this thread, but I just came across it(!). I just want anyone reading to know that the offset addresses, minor/major-loop counters, and half-full interrupts in the Kinetis DMA allow that DMA engine to FULLY deinterleave the I2S/SAI timeslot information into individual double-buffered linear sample arrays (arranged as a contiguous block) with no CPU overhead. See my original port on this. As pointed out in other discussions, this whole arrangement of timeslots thru the I2S/SAI FIFO interface relies on matching count operations at both the source and destination, but it works very nicely!

Re: I2S time slots and DMA buffers

bosleymusic_com — Wed, 12 Nov 2014 15:08:44 GMT

Can you provide a link to your original post on this. I'd like to see it, and couldn't find it among your activity.

Re: I2S time slots and DMA buffers

egoodii — Wed, 12 Nov 2014 15:47:38 GMT

I don't use PE, and my 'demo' is not for Version 2 silicon, but you should still get some ideas on how to use DMA to create double-buffer linear data areas:

is there any demo code for using I2S?