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    <title>Processor Expert Software中的主题 Ethernet component clock gating bug</title>
    <link>https://community.nxp.com/t5/Processor-Expert-Software/Ethernet-component-clock-gating-bug/m-p/354418#M2709</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;When running init method of ethernet LDD, a hard fault occurs due to missing clock gating of a port.&lt;/P&gt;&lt;P&gt;This can be reproduced easily and a test program is attached.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Processor Expert Driver Suite 10.4.1 was used together with IAR 7.30.1.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;/Peter&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* THIS WILL FAIL IN ETH1 LINE 231 DUE TO PORT CLOCK NOT SET */&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* The following two lines fixes it if uncommented */&lt;/P&gt;&lt;P&gt;//&amp;nbsp; /* SIM_SCGC5: PORTB=1 */&lt;/P&gt;&lt;P&gt;//&amp;nbsp; SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;&lt;/P&gt;&lt;P&gt;&amp;nbsp; device = ETH1_Init(NULL);&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="16815_16815.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/120032iFA642EECAE00530A/image-size/large?v=v2&amp;amp;px=999" role="button" title="16815_16815.jpg" alt="16815_16815.jpg" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="Build.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/47436iF164DBC06BF05345/image-size/large?v=v2&amp;amp;px=999" role="button" title="Build.jpg" alt="Build.jpg" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="16816_16816.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/120033iEE815098D33F4300/image-size/large?v=v2&amp;amp;px=999" role="button" title="16816_16816.jpg" alt="16816_16816.jpg" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="DebuggerAtError.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/47437iE83D3B7E8F38C73C/image-size/large?v=v2&amp;amp;px=999" role="button" title="DebuggerAtError.jpg" alt="DebuggerAtError.jpg" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="16817_16817.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/120034iC3D1AD9EF2834791/image-size/large?v=v2&amp;amp;px=999" role="button" title="16817_16817.jpg" alt="16817_16817.jpg" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="DebuggerAtInstructionCausingError.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/47438i91A133C499B00CB6/image-size/large?v=v2&amp;amp;px=999" role="button" title="DebuggerAtInstructionCausingError.jpg" alt="DebuggerAtInstructionCausingError.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Original Attachment has been moved to: &lt;A _jive_internal="true" href="https://community.nxp.com/docs/DOC-338599"&gt;ETH_K64.zip&lt;/A&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 19 Nov 2014 14:55:22 GMT</pubDate>
    <dc:creator>PeterFromSweden</dc:creator>
    <dc:date>2014-11-19T14:55:22Z</dc:date>
    <item>
      <title>Ethernet component clock gating bug</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/Ethernet-component-clock-gating-bug/m-p/354418#M2709</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;When running init method of ethernet LDD, a hard fault occurs due to missing clock gating of a port.&lt;/P&gt;&lt;P&gt;This can be reproduced easily and a test program is attached.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Processor Expert Driver Suite 10.4.1 was used together with IAR 7.30.1.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;/Peter&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* THIS WILL FAIL IN ETH1 LINE 231 DUE TO PORT CLOCK NOT SET */&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* The following two lines fixes it if uncommented */&lt;/P&gt;&lt;P&gt;//&amp;nbsp; /* SIM_SCGC5: PORTB=1 */&lt;/P&gt;&lt;P&gt;//&amp;nbsp; SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;&lt;/P&gt;&lt;P&gt;&amp;nbsp; device = ETH1_Init(NULL);&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="16815_16815.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/120032iFA642EECAE00530A/image-size/large?v=v2&amp;amp;px=999" role="button" title="16815_16815.jpg" alt="16815_16815.jpg" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="Build.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/47436iF164DBC06BF05345/image-size/large?v=v2&amp;amp;px=999" role="button" title="Build.jpg" alt="Build.jpg" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="16816_16816.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/120033iEE815098D33F4300/image-size/large?v=v2&amp;amp;px=999" role="button" title="16816_16816.jpg" alt="16816_16816.jpg" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="DebuggerAtError.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/47437iE83D3B7E8F38C73C/image-size/large?v=v2&amp;amp;px=999" role="button" title="DebuggerAtError.jpg" alt="DebuggerAtError.jpg" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="16817_16817.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/120034iC3D1AD9EF2834791/image-size/large?v=v2&amp;amp;px=999" role="button" title="16817_16817.jpg" alt="16817_16817.jpg" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="DebuggerAtInstructionCausingError.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/47438i91A133C499B00CB6/image-size/large?v=v2&amp;amp;px=999" role="button" title="DebuggerAtInstructionCausingError.jpg" alt="DebuggerAtInstructionCausingError.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Original Attachment has been moved to: &lt;A _jive_internal="true" href="https://community.nxp.com/docs/DOC-338599"&gt;ETH_K64.zip&lt;/A&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 19 Nov 2014 14:55:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/Ethernet-component-clock-gating-bug/m-p/354418#M2709</guid>
      <dc:creator>PeterFromSweden</dc:creator>
      <dc:date>2014-11-19T14:55:22Z</dc:date>
    </item>
    <item>
      <title>Re: Ethernet component clock gating bug</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/Ethernet-component-clock-gating-bug/m-p/354419#M2710</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Peter,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I just import your project to&amp;nbsp; PE suite 10.4, there are build errors.&lt;/P&gt;&lt;P&gt;do you use Processor Expert Driver Suite 10.4.1 with IAR?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Zhang Jun&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 21 Nov 2014 08:50:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/Ethernet-component-clock-gating-bug/m-p/354419#M2710</guid>
      <dc:creator>ZhangJennie</dc:creator>
      <dc:date>2014-11-21T08:50:37Z</dc:date>
    </item>
    <item>
      <title>Re: Ethernet component clock gating bug</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/Ethernet-component-clock-gating-bug/m-p/354420#M2711</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, I use IAR. Please find further info in updated orignal post.&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;/Peter&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 21 Nov 2014 09:42:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/Ethernet-component-clock-gating-bug/m-p/354420#M2711</guid>
      <dc:creator>PeterFromSweden</dc:creator>
      <dc:date>2014-11-21T09:42:36Z</dc:date>
    </item>
    <item>
      <title>Re: Ethernet component clock gating bug</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/Ethernet-component-clock-gating-bug/m-p/354421#M2712</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Peter,&lt;/P&gt;&lt;P&gt;I have reproduced the error - there is missing initialization of port clock gate in the Ethernet component. Thank you for reporting this error. It will be fixed in the next release of Processor Expert (update).&lt;BR /&gt;You can use the code (you have stated above) in the Ethernet Init() fuction as a workaroud. When you modify the Init() function it is receomended to freze the generated code of the component in the Processor Expert (open the context menu of the Ethernet component in Processor Expert project and select &lt;EM&gt;Code Generation - &amp;gt; Don't Write Generated Component Modules).&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;/* SIM_SCGC5: PORTB=1 */&lt;/P&gt;&lt;P&gt;SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Marek Neuzil&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Nov 2014 14:38:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/Ethernet-component-clock-gating-bug/m-p/354421#M2712</guid>
      <dc:creator>marek_neuzil</dc:creator>
      <dc:date>2014-11-25T14:38:16Z</dc:date>
    </item>
    <item>
      <title>Re: Re: Ethernet component clock gating bug</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/Ethernet-component-clock-gating-bug/m-p/354422#M2713</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;There is available hot fix of the Ethernet_LDD component, see the attached file.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Marek Neuzil&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 15 Dec 2014 12:34:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/Ethernet-component-clock-gating-bug/m-p/354422#M2713</guid>
      <dc:creator>marek_neuzil</dc:creator>
      <dc:date>2014-12-15T12:34:04Z</dc:date>
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