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    <title>Processor Expert Software中的主题 Re: SPI slave using PE: detecting start and end of frame</title>
    <link>https://community.nxp.com/t5/Processor-Expert-Software/SPI-slave-using-PE-detecting-start-and-end-of-frame/m-p/329177#M2507</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I find K12’s RM, there are some description for SPI slave&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;40.4.2.2 Slave mode&lt;/P&gt;&lt;P&gt;In SPI Slave mode the module responds to transfers initiated by an SPI bus master. It&lt;/P&gt;&lt;P&gt;does not initiate transfers. Certain transfer attributes such as clock polarity, clock phase,&lt;/P&gt;&lt;P&gt;and frame size must be set for successful communication with an SPI master. The SPI&lt;/P&gt;&lt;P&gt;Slave mode transfer attributes are set in the CTAR0 . The data is shifted out with MSB&lt;/P&gt;&lt;P&gt;first. Shifting out of LSB is not supported in this mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Dawei You（尤大为）&lt;/P&gt;&lt;P&gt;Mobile: +86 13675169919&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 03 Aug 2014 04:28:18 GMT</pubDate>
    <dc:creator>daweiyou</dc:creator>
    <dc:date>2014-08-03T04:28:18Z</dc:date>
    <item>
      <title>SPI slave using PE: detecting start and end of frame</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/SPI-slave-using-PE-detecting-start-and-end-of-frame/m-p/329176#M2506</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm using PE to access SPI slave.&lt;/P&gt;&lt;P&gt;The problem is that I would like to know which byte is the first after CS goes low.&lt;/P&gt;&lt;P&gt;As far as I saw, PE doesn't support such a feature, it just receives bytes from the SPI and accumulates them.&lt;/P&gt;&lt;P&gt;Also looking at the SPI datasheet, didn't see that such an option is supported by the hardware.&lt;/P&gt;&lt;P&gt;I need it to simplify communication synchronization, so that I'll be sure each time a new message is starting.&lt;/P&gt;&lt;P&gt;I'm using the MK11DN512VMC5 processor.&lt;/P&gt;&lt;P&gt;Am I missing something here?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks, Isak.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 Jul 2014 19:21:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/SPI-slave-using-PE-detecting-start-and-end-of-frame/m-p/329176#M2506</guid>
      <dc:creator>isaklevinson</dc:creator>
      <dc:date>2014-07-31T19:21:40Z</dc:date>
    </item>
    <item>
      <title>Re: SPI slave using PE: detecting start and end of frame</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/SPI-slave-using-PE-detecting-start-and-end-of-frame/m-p/329177#M2507</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I find K12’s RM, there are some description for SPI slave&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;40.4.2.2 Slave mode&lt;/P&gt;&lt;P&gt;In SPI Slave mode the module responds to transfers initiated by an SPI bus master. It&lt;/P&gt;&lt;P&gt;does not initiate transfers. Certain transfer attributes such as clock polarity, clock phase,&lt;/P&gt;&lt;P&gt;and frame size must be set for successful communication with an SPI master. The SPI&lt;/P&gt;&lt;P&gt;Slave mode transfer attributes are set in the CTAR0 . The data is shifted out with MSB&lt;/P&gt;&lt;P&gt;first. Shifting out of LSB is not supported in this mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Dawei You（尤大为）&lt;/P&gt;&lt;P&gt;Mobile: +86 13675169919&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 03 Aug 2014 04:28:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/SPI-slave-using-PE-detecting-start-and-end-of-frame/m-p/329177#M2507</guid>
      <dc:creator>daweiyou</dc:creator>
      <dc:date>2014-08-03T04:28:18Z</dc:date>
    </item>
    <item>
      <title>Re: SPI slave using PE: detecting start and end of frame</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/SPI-slave-using-PE-detecting-start-and-end-of-frame/m-p/329178#M2508</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Dawel,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Unfortunately, it doesn't help me.&lt;/P&gt;&lt;P&gt;I can successfully receive and transmit bytes by the SPI interface.&lt;/P&gt;&lt;P&gt;What I can't do, is to detect which of the received bytes is the first one in the frame (the firtst byte right after CS assertion).&lt;/P&gt;&lt;P&gt;It this supported in the SPI hardware, or will I have to do some "workearound tricks" to overcome it?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 03 Aug 2014 05:38:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/SPI-slave-using-PE-detecting-start-and-end-of-frame/m-p/329178#M2508</guid>
      <dc:creator>isaklevinson</dc:creator>
      <dc:date>2014-08-03T05:38:49Z</dc:date>
    </item>
    <item>
      <title>Re: SPI slave using PE: detecting start and end of frame</title>
      <link>https://community.nxp.com/t5/Processor-Expert-Software/SPI-slave-using-PE-detecting-start-and-end-of-frame/m-p/329179#M2509</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Isak,&lt;/P&gt;&lt;P&gt;As was mentioned by Dawel, the SPI device does not support selection of MSB/LSB in the SLAVE mode. There is supported the MSB first (Most Significant Bit first) in the SLAVE mode only, see details below:&lt;/P&gt;&lt;P&gt; &lt;span class="lia-inline-image-display-wrapper" image-alt="MSB_LSB_SPI.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/45564i7A3414437A5ADA94/image-size/large?v=v2&amp;amp;px=999" role="button" title="MSB_LSB_SPI.png" alt="MSB_LSB_SPI.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;You can see, that the in the Slave mode (MSB only) the bit 7 (MSB – Most Significant Bit) is send after CS and the bit 0 (Least Significant Bit) is send as the last bit,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;(for more details, see the reference manual&amp;nbsp; K11P121M50SF4RM, &lt;A href="http://cache.freescale.com/files/32bit/doc/ref_manual/K11P121M50SF4RM.pdf?fasp=1"&gt;http://cache.freescale.com/files/32bit/doc/ref_manual/K11P121M50SF4RM.pdf?fasp=1&lt;/A&gt;)&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Aug 2014 06:38:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Processor-Expert-Software/SPI-slave-using-PE-detecting-start-and-end-of-frame/m-p/329179#M2509</guid>
      <dc:creator>marek_neuzil</dc:creator>
      <dc:date>2014-08-11T06:38:22Z</dc:date>
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