topic Where is DMAMUX selector in DMA_LDD component? in Processor Expert Software

Where is DMAMUX selector in DMA_LDD component?

jackblather — Tue, 29 Jul 2014 01:29:35 GMT

I'm trying to set up DMA for SPI on the Vybrid.

So far, I have added the DMATransfer_LDD component. PEx automatically named this "DMAT1". I configured this to use with trigger source DMA_SPI2_Receive.

PEx automatically added the DMA_LDD component. I renamed it "DMA_0".

PEx automatically chose DMA channel "DMA0_Channel0" for component DMA_0. However, this caused the DMAT1 component to report the error, "No DMAMUX1 channel configured in DMA_0 component. Add DMAMUX1 channel in DMA_0 component."

The problem is that there is no way to select the DMAMUX channel in the DMA_0 component.

There is nothing about DMA channel and DMAMUX channel restrictions in the Vybrid Reference Manual. Chapter 22 (DMAMUX) in the Vybrid Reference manual mentions nothing about it. Tables 8-2 and 8-3 mention nothing about this, either.

The same error appears for DMA0_Channels 0 through 15. The error goes away if I chose any of the DMA0_Channels 16 through 31.

What are the rules for selecting DMA0 channels in the DMA_LDD component when used with the DMATransfer_LDD?

Thanks in Advance.

Re: Where is DMAMUX selector in DMA_LDD component?

michalvagner — Fri, 01 Aug 2014 12:34:42 GMT

SPI2 receive could be connected to the DMA1 (through MUX2) or to the DMA0 (through MUX1), see Table 8-2 in the RM.

Request from MUX2 can be mapped to any of the first 16 DMA1 channels and from MUX1 to any of the upper 16 DMA0 channels, see Figure 8-5.

Similarly, request from MUX3 can be mapped to any of the upper 16 DMA1 channels and from MUX0 to any of the first 16 DMA0 channels.

To use SPI2 receive trigger:

Go to the DMA component and select any channel from DMA1_Channel0 through DMA1_Channel15 if DMA1 device is used.

Or, use any channel from DMA0_Channel16 through DMA0_Channel31 if DMA0 device is used in the DMA_LDD,

Re: Where is DMAMUX selector in DMA_LDD component?

jackblather — Fri, 01 Aug 2014 16:21:46 GMT

I see how it works now. The use of "first" and "upper" term are ambiguous. The terms that should have been used are "first"/"last" or "lower"/"upper".

When "first"/"upper" are used, it seems these two terms are referring to the same DMA channels because the term "upper" could be taken to mean *top* DMA channels in the diagram graphic.

Instead, the intention was that "upper" means the higher-numbered channels when it looks like it could mean the *lower-numbered* channels in the graphic. The lower-numbered channels in the diagram are in the *upper* part of the DMA0/DMA1 blocks. This is where the confusion came from.

Another alternative is to label these terms in the diagram itself.

Thanks for the example you gave. It cleared things up.