topic Re: How important is it that the PE FIFO size for K60 SPI peripherals is wrong? in Processor Expert Software https://community.nxp.com/t5/Processor-Expert-Software/How-important-is-it-that-the-PE-FIFO-size-for-K60-SPI/m-p/238539#M1284 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P></P><P>I must confirm that this is really bug in latest version of PEx. However I think it should not influence code functionality. You can for example compare generated code when you set buffer size to 1 and to 16, the only difference is in DIS_TXF/DIS_RXF bitfields in MCR register. DIS_TXF/DIS_RXF bit-fields disable/enable FIFO -&gt; size 4 or 16 should not influence driver functionality.</P><P></P><P>We will fix it for next release of PEx.</P><P></P><P>We are sorry for inconvenience.</P><P></P><P>Best regards</P><P>Vojtech Filip</P><P>Processor Expert Support Team</P></BODY></HTML> Wed, 04 Dec 2013 10:30:41 GMT vfilip 2013-12-04T10:30:41Z How important is it that the PE FIFO size for K60 SPI peripherals is wrong? https://community.nxp.com/t5/Processor-Expert-Software/How-important-is-it-that-the-PE-FIFO-size-for-K60-SPI/m-p/238538#M1283 <HTML><HEAD></HEAD><BODY><P>I am running CW 10.5 Build 130916</P><P></P><P>I have generated SPI code for the K60DN512VMD10 chip (for SPI2)</P><P>In the attribute set list section, it will only accept 1 and 16 for both the HW input buffer size and the HW output buffer size.</P><P>This is incorrect (AFAICT), the values should be 1 or 4.</P><P></P><P>However, I am not sure this affects any of the generated code at all.</P><P></P><P>How important is this error?</P></BODY></HTML> Mon, 02 Dec 2013 18:01:42 GMT https://community.nxp.com/t5/Processor-Expert-Software/How-important-is-it-that-the-PE-FIFO-size-for-K60-SPI/m-p/238538#M1283 Symbolic 2013-12-02T18:01:42Z Re: How important is it that the PE FIFO size for K60 SPI peripherals is wrong? https://community.nxp.com/t5/Processor-Expert-Software/How-important-is-it-that-the-PE-FIFO-size-for-K60-SPI/m-p/238539#M1284 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P></P><P>I must confirm that this is really bug in latest version of PEx. However I think it should not influence code functionality. You can for example compare generated code when you set buffer size to 1 and to 16, the only difference is in DIS_TXF/DIS_RXF bitfields in MCR register. DIS_TXF/DIS_RXF bit-fields disable/enable FIFO -&gt; size 4 or 16 should not influence driver functionality.</P><P></P><P>We will fix it for next release of PEx.</P><P></P><P>We are sorry for inconvenience.</P><P></P><P>Best regards</P><P>Vojtech Filip</P><P>Processor Expert Support Team</P></BODY></HTML> Wed, 04 Dec 2013 10:30:41 GMT https://community.nxp.com/t5/Processor-Expert-Software/How-important-is-it-that-the-PE-FIFO-size-for-K60-SPI/m-p/238539#M1284 vfilip 2013-12-04T10:30:41Z