<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Corenet fabric speed in P-Series</title>
    <link>https://community.nxp.com/t5/P-Series/Corenet-fabric-speed/m-p/270510#M764</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: tahoma, arial, helvetica, sans-serif;"&gt;Hi All,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: tahoma, arial, helvetica, sans-serif; color: #000000;"&gt;In past, I think the FSB (Front Side Bus/Bus Speed) for any processor is computed against half the clock rate, so for e.g. 1.8 GHz processor with dual 32 Bit bus , both clocked at 450 Mhz. If I use the same concept here(p4080 -1.5 Ghz) in case of fabric and assume the fabric is accelerated @ ~750 Mhz .&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: tahoma, arial, helvetica, sans-serif; color: #000000;"&gt;Is this assumption right? It would be great, if someone can clarify how can we correlate the bus speed against fabric speed?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: tahoma, arial, helvetica, sans-serif; color: #000000;"&gt;Any specific document or reference link will also be helpful..&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: tahoma, arial, helvetica, sans-serif;"&gt;Thanks in Advance.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 22 Aug 2013 16:22:30 GMT</pubDate>
    <dc:creator>Simbu</dc:creator>
    <dc:date>2013-08-22T16:22:30Z</dc:date>
    <item>
      <title>Corenet fabric speed</title>
      <link>https://community.nxp.com/t5/P-Series/Corenet-fabric-speed/m-p/270510#M764</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: tahoma, arial, helvetica, sans-serif;"&gt;Hi All,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: tahoma, arial, helvetica, sans-serif; color: #000000;"&gt;In past, I think the FSB (Front Side Bus/Bus Speed) for any processor is computed against half the clock rate, so for e.g. 1.8 GHz processor with dual 32 Bit bus , both clocked at 450 Mhz. If I use the same concept here(p4080 -1.5 Ghz) in case of fabric and assume the fabric is accelerated @ ~750 Mhz .&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: tahoma, arial, helvetica, sans-serif; color: #000000;"&gt;Is this assumption right? It would be great, if someone can clarify how can we correlate the bus speed against fabric speed?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: tahoma, arial, helvetica, sans-serif; color: #000000;"&gt;Any specific document or reference link will also be helpful..&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: tahoma, arial, helvetica, sans-serif;"&gt;Thanks in Advance.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 22 Aug 2013 16:22:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Corenet-fabric-speed/m-p/270510#M764</guid>
      <dc:creator>Simbu</dc:creator>
      <dc:date>2013-08-22T16:22:30Z</dc:date>
    </item>
    <item>
      <title>Re: Corenet fabric speed</title>
      <link>https://community.nxp.com/t5/P-Series/Corenet-fabric-speed/m-p/270511#M765</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I found the below statement from P4080 product description &lt;A href="http://cache.freescale.com/files/32bit/doc/prod_brief/P4080PB.pdf?fpsp=1"&gt;link&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;Power management is always a major design consideration in embedded applications, and for this reason, &lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;the P4080 is designed to dissipate &amp;lt;30 W Max with all 8 CPUs and platform logic running at maximum &lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;frequency (8x 1.5 GHz CPUs, 800 MHz CoreNet).&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does this mean that the corenet speed as such one and can't be described against single core like speed/core ??&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in Advance.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 23 Aug 2013 05:54:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Corenet-fabric-speed/m-p/270511#M765</guid>
      <dc:creator>Simbu</dc:creator>
      <dc:date>2013-08-23T05:54:29Z</dc:date>
    </item>
    <item>
      <title>Re: Corenet fabric speed</title>
      <link>https://community.nxp.com/t5/P-Series/Corenet-fabric-speed/m-p/270512#M766</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks.. I got the answer from U boot log and from the uboot code &lt;SPAN style="color: #444444; font-family: arial, sans-serif; font-size: small;"&gt;freqSystemBus&lt;/SPAN&gt;.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Aug 2013 06:59:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Corenet-fabric-speed/m-p/270512#M766</guid>
      <dc:creator>Simbu</dc:creator>
      <dc:date>2013-08-27T06:59:56Z</dc:date>
    </item>
  </channel>
</rss>

