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    <title>P-SeriesのトピックP3041 cores disable</title>
    <link>https://community.nxp.com/t5/P-Series/P3041-cores-disable/m-p/261680#M656</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In my application, I may use just one from the 4 cores of the P3041. Can I disable the unused cores, in order to save power? Does anybody have a power estimation for not using all of the cores?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance&lt;/P&gt;&lt;P&gt;Victor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 28 May 2013 21:03:47 GMT</pubDate>
    <dc:creator>victorjardim</dc:creator>
    <dc:date>2013-05-28T21:03:47Z</dc:date>
    <item>
      <title>P3041 cores disable</title>
      <link>https://community.nxp.com/t5/P-Series/P3041-cores-disable/m-p/261680#M656</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In my application, I may use just one from the 4 cores of the P3041. Can I disable the unused cores, in order to save power? Does anybody have a power estimation for not using all of the cores?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance&lt;/P&gt;&lt;P&gt;Victor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 May 2013 21:03:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P3041-cores-disable/m-p/261680#M656</guid>
      <dc:creator>victorjardim</dc:creator>
      <dc:date>2013-05-28T21:03:47Z</dc:date>
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    <item>
      <title>Re: P3041 cores disable</title>
      <link>https://community.nxp.com/t5/P-Series/P3041-cores-disable/m-p/261681#M657</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Victor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;As far I know if you don't enable them in BRR register they are not enabled - so you can check the BRR register -&amp;gt; 0xe00e4 offset and you can disable the rest of the cores.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I can't provide a power estimation for this case, but you can take a look in the Reference Manual for P3041 at "Advanced Power Management" chapter and read about "Saving Power by Managing Internal Clocks" (1.9.1) and also about&amp;nbsp;&amp;nbsp; "Turning Off Unneeded Clocks".&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Marius&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 May 2013 06:51:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P3041-cores-disable/m-p/261681#M657</guid>
      <dc:creator>marius_grigoras</dc:creator>
      <dc:date>2013-05-29T06:51:59Z</dc:date>
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    <item>
      <title>Re: P3041 cores disable</title>
      <link>https://community.nxp.com/t5/P-Series/P3041-cores-disable/m-p/261682#M658</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Victor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Some comment from application team for your information:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="EN-US" style="font-size: 10pt; font-family: arial,helvetica,sans-serif;"&gt;COREDISR prevents a core from receiving any clocks whatsoever. Boot Release Register is intended to be used to sequence when to allow a core to begin booting (so initial SoC configuration may be done with one CPU and once that is complete the others begin for example). If a CPU is disabled with COREDISR, it should never be released with BRR - that is not valid. A core which is intended never to be used should be disabled with COREDISR, as this should save a small amount of additional power compared to having its COREDISR enabled but not releasing it for booting.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 03 Jun 2013 01:34:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P3041-cores-disable/m-p/261682#M658</guid>
      <dc:creator>lunminliang</dc:creator>
      <dc:date>2013-06-03T01:34:00Z</dc:date>
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