topic Re: P2010 - PLLs problem in P-Series https://community.nxp.com/t5/P-Series/P2010-PLLs-problem/m-p/259686#M593 <HTML><HEAD></HEAD><BODY><P>Great new! I've found what was the problem.</P><P>The problem was that the clock source of the SYCLK pin was not compliant with the specifications of the rise/fall time required for the P2010. Changing the clock buffer with a better rise/fall time the problem was solved. Now the CPU works as expected and every options work as required.</P></BODY></HTML> Fri, 21 Jun 2013 13:06:00 GMT marcosantos 2013-06-21T13:06:00Z P2010 - PLLs problem https://community.nxp.com/t5/P-Series/P2010-PLLs-problem/m-p/259682#M589 <HTML><HEAD></HEAD><BODY><P>In my board, the P2010 has problems with the internal PLLs. The SYSCLK is 66.6666MHz and the CCB ratio is 8:1 but I get about 1GHz at the CLK_OUT pin if I select in GUTS_CLKOCR=0x80000000. What is even more strange is the I got about 58MHz at CLK_OUT pin if I choose GUTS_CLKOCR=0x80000003 and not 33MHz. What is even more stange is that the 8:1 ratio of the CCB should be 533MHz (8x66=533) but if I choose the 4:1 CCB ratio I got 533MHz! Another very strange thing is that the GUTS_PORPLLSR register shows correct ratios but the clocks doesn't match what the register says. But, the GUTS_PORPLLSR register also has some strange things. In the reference manual the figure of this register shows 5 bits for the DDR_RATIO but the describing text shows 6 bits.</P><P>Anyone where experience a similar problem? I already check every clock, voltage and bootstrap and every thing looks okay. </P></BODY></HTML> Wed, 10 Apr 2013 09:36:03 GMT https://community.nxp.com/t5/P-Series/P2010-PLLs-problem/m-p/259682#M589 marcosantos 2013-04-10T09:36:03Z Re: P2010 - PLLs problem https://community.nxp.com/t5/P-Series/P2010-PLLs-problem/m-p/259683#M590 <HTML><HEAD></HEAD><BODY><P>Please see below comment from technical support:</P><P></P><P>Please confirm that when cfg_sys_pll[0:2]=011 the GUTS_PORPLLSR[Plat_Ratio]=01000.</P><P>Please provide the processor connection schematics for inspection as searchable PDF. (You can send direct message to me for this part)</P><P>DDR_Ratio field has 5 bits. Please take into account the last 5 digits in the description.</P><P><SPAN class="mce_paste_marker"><BR /></SPAN></P></BODY></HTML> Wed, 24 Apr 2013 06:50:32 GMT https://community.nxp.com/t5/P-Series/P2010-PLLs-problem/m-p/259683#M590 lunminliang 2013-04-24T06:50:32Z Re: P2010 - PLLs problem https://community.nxp.com/t5/P-Series/P2010-PLLs-problem/m-p/259684#M591 <HTML><HEAD></HEAD><BODY><P>I verified that if cfg_sys_pll[0:2]=011 then GUTS_PORPLLSR[Plat_Ratio]=01000.</P></BODY></HTML> Wed, 24 Apr 2013 09:49:31 GMT https://community.nxp.com/t5/P-Series/P2010-PLLs-problem/m-p/259684#M591 marcosantos 2013-04-24T09:49:31Z Re: P2010 - PLLs problem https://community.nxp.com/t5/P-Series/P2010-PLLs-problem/m-p/259685#M592 <HTML><HEAD></HEAD><BODY><P>It could be helpful to provide the processor connection schematics for inspection as searchable PDF. Direct message could be used.</P></BODY></HTML> Sun, 28 Apr 2013 06:07:36 GMT https://community.nxp.com/t5/P-Series/P2010-PLLs-problem/m-p/259685#M592 lunminliang 2013-04-28T06:07:36Z Re: P2010 - PLLs problem https://community.nxp.com/t5/P-Series/P2010-PLLs-problem/m-p/259686#M593 <HTML><HEAD></HEAD><BODY><P>Great new! I've found what was the problem.</P><P>The problem was that the clock source of the SYCLK pin was not compliant with the specifications of the rise/fall time required for the P2010. Changing the clock buffer with a better rise/fall time the problem was solved. Now the CPU works as expected and every options work as required.</P></BODY></HTML> Fri, 21 Jun 2013 13:06:00 GMT https://community.nxp.com/t5/P-Series/P2010-PLLs-problem/m-p/259686#M593 marcosantos 2013-06-21T13:06:00Z