https://community.nxp.com/t5/P-Series/How-to-disable-L2-cache-on-P1022DS/m-p/251460#M510 <HTML><HEAD></HEAD><BODY><P>I am afraid there is no option to do this except modify the source code.</P></BODY></HTML> Sun, 07 Apr 2013 07:37:09 GMT lunminliang 2013-04-07T07:37:09Z https://community.nxp.com/t5/P-Series/How-to-disable-L2-cache-on-P1022DS/m-p/251459#M509 <HTML><HEAD></HEAD><BODY><P>We are now utilizing our P1022 developent systems (P1022DS) for software component testing (unit/module testing).</P><P></P><P>We would like to extend these tests to include execution time measurements. The L2-cache is disabled in our target system, so in order to get comparable values we need to disable it for the Linux system running on the P1022DS as well. How do we proceed to achieve this?</P><P></P><P>(We use a proprietary OS for our target system, so - apparently - we lack the necessary expertise in Linux.)</P></BODY></HTML> Thu, 04 Apr 2013 15:41:48 GMT https://community.nxp.com/t5/P-Series/How-to-disable-L2-cache-on-P1022DS/m-p/251459#M509 perrub 2013-04-04T15:41:48Z https://community.nxp.com/t5/P-Series/How-to-disable-L2-cache-on-P1022DS/m-p/251460#M510 <HTML><HEAD></HEAD><BODY><P>I am afraid there is no option to do this except modify the source code.</P></BODY></HTML> Sun, 07 Apr 2013 07:37:09 GMT https://community.nxp.com/t5/P-Series/How-to-disable-L2-cache-on-P1022DS/m-p/251460#M510 lunminliang 2013-04-07T07:37:09Z https://community.nxp.com/t5/P-Series/How-to-disable-L2-cache-on-P1022DS/m-p/251461#M511 <HTML><HEAD></HEAD><BODY><P><BR />I was hoping for a more convenient way, but I didn't really expect it...</P><P></P><P>From the reference manual: The L2 cache is disabled by setting L2 enable (L2E, bit 0) of the L2 Control Register (L2CTL) to 0. L2CTL is memory mapped at an offset of 0x20000 from the Configuration, Control, and Status Register Base Address.</P><P></P><UL><LI>How do we find out which Base Address our system use?</LI><LI>How do we actually access the L2CTL register? I suspect we need user privileges of some kind, and perhaps some kind of address processing (remapping)...?</LI></UL></BODY></HTML> Mon, 15 Apr 2013 05:49:54 GMT https://community.nxp.com/t5/P-Series/How-to-disable-L2-cache-on-P1022DS/m-p/251461#M511 perrub 2013-04-15T05:49:54Z https://community.nxp.com/t5/P-Series/How-to-disable-L2-cache-on-P1022DS/m-p/251462#M512 <HTML><HEAD></HEAD><BODY><P>We ended up writing a loadable kernel module, with the core part being these rows:</P><P></P><P style="padding-left: 30px;"><SPAN style="font-family: courier new,courier;">phys_addr_t L2CTL = get_immrbase() + 0x20000;</SPAN></P><P style="padding-left: 30px;"><SPAN style="font-family: courier new,courier;">void* L2_controller = ioremap_nocache(L2CTL, 4);</SPAN></P><P style="padding-left: 30px;"><SPAN style="font-family: courier new,courier;">iowrite8(0x50, L2_controller);</SPAN></P><P></P><P><SPAN style="font-family: arial,helvetica,sans-serif;">This seems to do the trick for us.</SPAN></P></BODY></HTML> Wed, 17 Apr 2013 09:07:54 GMT https://community.nxp.com/t5/P-Series/How-to-disable-L2-cache-on-P1022DS/m-p/251462#M512 perrub 2013-04-17T09:07:54Z