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    <title>P-Series中的主题 Unpredictable IRQ6 behaviour on P1022 based target</title>
    <link>https://community.nxp.com/t5/P-Series/Unpredictable-IRQ6-behaviour-on-P1022-based-target/m-p/1043178#M4845</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="margin: 0cm 0cm 10pt; font-size: 11pt;"&gt;We have a target based on P1022.&lt;/P&gt;&lt;P style="margin: 0cm 0cm 10pt; font-size: 11pt;"&gt;IRQ6 line of Processor is connected to CPLD. Line is pulled up by default.&lt;/P&gt;&lt;P style="margin: 0cm 0cm 10pt; font-size: 11pt;"&gt;Observation &amp;nbsp;1 : This line is being driven high permanently from CPLD. Still there are spurious interrupts seen on IRQ6 line in processor which are also increasing in a random manner. Interrupt is edge triggered (high to low)&lt;/P&gt;&lt;P style="margin: 0cm 0cm 10pt; font-size: 11pt;"&gt;Observation 2 : To track the status of line internally. We configured the interrupt line as input in CPLD.&amp;nbsp; Still there were spurious interrupts seen in Processor but we did not detect any change in digital level input of this line in CPLD. No change from 1 to 0 was triggered in CPLD. CPLD always received the line as high input.&lt;/P&gt;&lt;P style="margin: 0cm 0cm 10pt; font-size: 11pt;"&gt;The device tree node configuration for corresponding interrupt is -&lt;/P&gt;&lt;P&gt;ext_irq6{&lt;BR /&gt; interrupt-parent = &amp;lt;&amp;amp;mpic&amp;gt;;&lt;BR /&gt; interrupts = &amp;lt;6 3 0 0&amp;gt;;&lt;/P&gt;&lt;P&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please suggest to identify the issue.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Ram&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 20 May 2020 05:49:15 GMT</pubDate>
    <dc:creator>rammurmu</dc:creator>
    <dc:date>2020-05-20T05:49:15Z</dc:date>
    <item>
      <title>Unpredictable IRQ6 behaviour on P1022 based target</title>
      <link>https://community.nxp.com/t5/P-Series/Unpredictable-IRQ6-behaviour-on-P1022-based-target/m-p/1043178#M4845</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="margin: 0cm 0cm 10pt; font-size: 11pt;"&gt;We have a target based on P1022.&lt;/P&gt;&lt;P style="margin: 0cm 0cm 10pt; font-size: 11pt;"&gt;IRQ6 line of Processor is connected to CPLD. Line is pulled up by default.&lt;/P&gt;&lt;P style="margin: 0cm 0cm 10pt; font-size: 11pt;"&gt;Observation &amp;nbsp;1 : This line is being driven high permanently from CPLD. Still there are spurious interrupts seen on IRQ6 line in processor which are also increasing in a random manner. Interrupt is edge triggered (high to low)&lt;/P&gt;&lt;P style="margin: 0cm 0cm 10pt; font-size: 11pt;"&gt;Observation 2 : To track the status of line internally. We configured the interrupt line as input in CPLD.&amp;nbsp; Still there were spurious interrupts seen in Processor but we did not detect any change in digital level input of this line in CPLD. No change from 1 to 0 was triggered in CPLD. CPLD always received the line as high input.&lt;/P&gt;&lt;P style="margin: 0cm 0cm 10pt; font-size: 11pt;"&gt;The device tree node configuration for corresponding interrupt is -&lt;/P&gt;&lt;P&gt;ext_irq6{&lt;BR /&gt; interrupt-parent = &amp;lt;&amp;amp;mpic&amp;gt;;&lt;BR /&gt; interrupts = &amp;lt;6 3 0 0&amp;gt;;&lt;/P&gt;&lt;P&gt;};&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please suggest to identify the issue.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Ram&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 May 2020 05:49:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Unpredictable-IRQ6-behaviour-on-P1022-based-target/m-p/1043178#M4845</guid>
      <dc:creator>rammurmu</dc:creator>
      <dc:date>2020-05-20T05:49:15Z</dc:date>
    </item>
    <item>
      <title>Re: Unpredictable IRQ6 behaviour on P1022 based target</title>
      <link>https://community.nxp.com/t5/P-Series/Unpredictable-IRQ6-behaviour-on-P1022-based-target/m-p/1043179#M4846</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN&gt;Please provide value of the &lt;/SPAN&gt;PIC_EIVPR6.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please use a digital scope and capture trace of the IRQ6 pin voltage behaviour.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Isn't the IRQ6 shared with PCI Express 2 INTC?&lt;BR /&gt;Refer to the P1022 QorIQ Integrated Processor Reference Manual, 10.4.6 PCI Express INTx/IRQn sharing.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 May 2020 08:19:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Unpredictable-IRQ6-behaviour-on-P1022-based-target/m-p/1043179#M4846</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2020-05-20T08:19:15Z</dc:date>
    </item>
    <item>
      <title>Re: Unpredictable IRQ6 behaviour on P1022 based target</title>
      <link>https://community.nxp.com/t5/P-Series/Unpredictable-IRQ6-behaviour-on-P1022-based-target/m-p/1043180#M4847</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Value of PIC_EIVPR6 is &lt;STRONG&gt;0x80006&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I will update the rest of query in my subsequent reply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 May 2020 09:12:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Unpredictable-IRQ6-behaviour-on-P1022-based-target/m-p/1043180#M4847</guid>
      <dc:creator>rammurmu</dc:creator>
      <dc:date>2020-05-20T09:12:45Z</dc:date>
    </item>
    <item>
      <title>Re: Unpredictable IRQ6 behaviour on P1022 based target</title>
      <link>https://community.nxp.com/t5/P-Series/Unpredictable-IRQ6-behaviour-on-P1022-based-target/m-p/1043181#M4848</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV class="" style="font-family: arial,sans-serif; font-size: small; color: #073763;"&gt;As I understand from section 10.4.6, there is sharing between INTx and IRQn. The sharing is implemented in Hardware and can not be disabled.&lt;/DIV&gt;&lt;DIV class="" style="font-family: arial,sans-serif; font-size: small; color: #073763;"&gt;&lt;/DIV&gt;&lt;DIV class="" style="font-family: arial,sans-serif; font-size: small; color: #073763;"&gt;The only option left is to disable the corresponding PCIe interrupt to correctly use external IRQ6.&lt;/DIV&gt;&lt;DIV class="" style="font-family: arial,sans-serif; font-size: small; color: #073763;"&gt;&lt;/DIV&gt;&lt;DIV class="" style="font-family: arial,sans-serif; font-size: small; color: #073763;"&gt;I need to use external IRQ6, therefore to stop PCIe interrupts from coming on same IRQ(IRQ6) line, INTC interrupt line for PCI Express Controller-2 need to be disabled.&lt;/DIV&gt;&lt;DIV class="" style="font-family: arial,sans-serif; font-size: small; color: #073763;"&gt;&lt;/DIV&gt;&lt;DIV class="" style="font-family: arial,sans-serif; font-size: small; color: #073763;"&gt;Any feedback to disable the same or any section in Ref. Manual that suggests how to disable the INTC interrupt line for PCIe2, so that I can use external IRQ6 correctly, my please be shared.&lt;/DIV&gt;&lt;DIV class="" style="font-family: arial,sans-serif; font-size: small; color: #073763;"&gt;&lt;/DIV&gt;&lt;DIV class="" style="font-family: arial,sans-serif; font-size: small; color: #073763;"&gt;Thanks&lt;/DIV&gt;&lt;DIV class="" style="font-family: arial,sans-serif; font-size: small; color: #073763;"&gt;Ram&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 28 May 2020 00:47:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Unpredictable-IRQ6-behaviour-on-P1022-based-target/m-p/1043181#M4848</guid>
      <dc:creator>rammurmu</dc:creator>
      <dc:date>2020-05-28T00:47:38Z</dc:date>
    </item>
    <item>
      <title>Re: Unpredictable IRQ6 behaviour on P1022 based target</title>
      <link>https://community.nxp.com/t5/P-Series/Unpredictable-IRQ6-behaviour-on-P1022-based-target/m-p/1043182#M4849</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;To disable interrupt from an external PCIe device it is needed to refer to the device documentation.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 28 May 2020 05:03:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Unpredictable-IRQ6-behaviour-on-P1022-based-target/m-p/1043182#M4849</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2020-05-28T05:03:42Z</dc:date>
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