topic Re: P1022 TLB entries in P-Series

P1022 TLB entries

sujanathinaraya — Tue, 04 Feb 2020 05:21:12 GMT

Hi,

I am working on P1022 board. In that tlb.c file, I have seen below TLB0 entries ( CONFIG_SYS_INIT_RAM_ADDR - 0xffd00000, size - 16K) .please explain me the pupose of this 16K temp stack in cache.

/* TLB 0 - for temp stack in cache */
 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 MAS3_SX|MAS3_SW|MAS3_SR, 0,
 0, 0, BOOKE_PAGESZ_4K, 0),
 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 MAS3_SX|MAS3_SW|MAS3_SR, 0,
 0, 0, BOOKE_PAGESZ_4K, 0),
 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 MAS3_SX|MAS3_SW|MAS3_SR, 0,
 0, 0, BOOKE_PAGESZ_4K, 0),
 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 MAS3_SX|MAS3_SW|MAS3_SR, 0,
 0, 0, BOOKE_PAGESZ_4K, 0),

Re: P1022 TLB entries

ufedor — Tue, 04 Feb 2020 11:43:33 GMT

Please consider that CONFIG_SYS_INIT_RAM_ADDR is:

Start address of memory area that can be used for initial data and stack; please note that this must be writable memory that is working WITHOUT special initialization, i. e. you CANNOT use normal RAM which will become available only after programming the memory controller and running certain initialization sequences.

Refer to the Start.s:

u-boot/start.S at b3f98d438eefd1b355efdec0b50af5813ff8d0e1 · qoriq-open-source/u-boot · GitHub

/* L1 DCache is used for initial RAM */

Re: P1022 TLB entries

sujanathinaraya — Tue, 04 Feb 2020 13:11:28 GMT

Thank you ufedor for your valuable reply. I understand that CONFIG_SYS_INIT_RAM_ADDR is configured as L1 data cache to execute program before initialization of normal ram. Whether CONFIG_SYS_INIT_RAM_ADDR address and size is configurable? i.e any address and size can be used instead of 0xffd00000 and 16k size.

Re: P1022 TLB entries

sujanathinaraya — Tue, 04 Feb 2020 13:22:48 GMT

Hi,

Re: P1022 TLB entries

ufedor — Tue, 04 Feb 2020 13:30:19 GMT

> any address and size can be used instead of 0xffd00000 and 16k size.

The address should not interfere with the final memory map.

Re: P1022 TLB entries

sujanathinaraya — Tue, 04 Feb 2020 13:46:35 GMT

How this address is configured as L1 data cache address?

More than 32kb size can i configure?

Re: P1022 TLB entries

ufedor — Tue, 04 Feb 2020 14:30:33 GMT

> How this address is configured as L1 data cache address?

Refer to the "Start.s" code.

> More than 32kb size can i configure?

Of course - not.

Re: P1022 TLB entries

sujanathinaraya — Tue, 04 Feb 2020 14:59:01 GMT

Thank you ufedor...