Using the cache line locking instructions

moncef_mechri — Wed, 28 Nov 2012 11:40:19 GMT

Hi everybody,

I'm trying to use the cache line locking instructions (like dcbtls) on a p4080 system running Linux but it doesn't seem to be working.

The code compiles just fine but I get an Illegal Instruction error at runtime.

I tried to imitate the way the linux kernel uses the dcbt instruction (see git.kernel.org - linux/kernel/git/torvalds/linux.git/blob - arch/powerpc/include/asm/processor.h ).

My only wild guess is that I do not have the right to execute this instruction since the doc says that MSR[UCLE] must be set for this instruction to be available to users. But I do not know how to check that.

Any idea?

Thanks!

Original Attachment has been moved to: lock_lines-(1).cpp.zip

Re: Using the cache line locking instructions

lunminliang — Wed, 17 Apr 2013 05:44:38 GMT

See below comment from technical support.

The following is said in e500mc Reference Manual:

The dcbtls, dcbtstls, dcblc, icbtls, and icblc cache-locking instructions require hypervisor state privilege to execute when MSRP[UCLEP] is set. Execution of these instructions in the guest supervisor state when MSRP[UCLEP] is set causes a hypervisor privilege exception. User mode execution of these instructions is unaffected and is still controlled by MSR[UCLE].

To check MSR[UCLE] you can read MSR register contents to any GPR register using "mfmsr" instruction.

The following is the definition of UCLE field from EREF Manual:

37 UCLE User-mode cache lock enable. <Embedded.Cache Locking> 0 - Any cache lock instruction executed in user-mode takes a cache-locking DSI exception and sets either ESR[DLK] or ESR[ILK]. This allows the operating system to manage and track the locking/unlocking of cache lines by user-mode tasks.

1 - Cache-locking instructions can be executed in user-mode and they do not take a DSI for cache-locking. (They may still take a DSI for access violations though.) MSR[UCLE] cannot be modified when MSR[GS]=1 unless MSRP[UCLEP] is 0. <Embedded.Hypervisor>

topic Re: Using the cache line locking instructions in P-Series

Using the cache line locking instructions

Re: Using the cache line locking instructions